ADP3203JRU-10-RL7 AD [Analog Devices], ADP3203JRU-10-RL7 Datasheet - Page 2

• Manufacturer Part Number: ADP3203JRU-10-RL7
• Description: 2-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs
• Manufacturer: AD [Analog Devices]

ADP3203–SPECIFICATIONS
DSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted) Current sunk by a pin has a positive sign, sourced by a pin has a
negative sign. Negative sign is disregarded for min and max values.
Parameter
SUPPLY-UVLO-SHUTDOWN
POWERGOOD-CORE FEEDBACK
SOFT-START/HICCUP TIMER
VID DAC
Notes:
1
2
3
4
5
6
7
Guaranteed by design.
Two test conditions: 1)PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V
the COREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking
delay time. 2) PWRGD is forced to fail (V
(V
blanking delay time.
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
Measured from 50% of VID code transition amplitude to the point where V
40 mV
Measured between the 30% and 70% points of the output voltage swing.
Guaranteed by characterization.
Normal Supply Current
UVLO Supply Current
Shutdown Supply Current
UVLO Threshold
UVLO Hysteresis
Shutdown Threshold (CMOS Input)
Core Feedback Threshold Voltage
Power Good Output Voltage
Masking Time
Charge/Discharge Current
Soft-Start Enable/Hiccup
Soft-Start Termination/Hiccup
VID Input Threshold (CMOS Inputs)
VID Input Current
Output Voltage
Accuracy
Settling Time
(open drain output)
COREFB,GOOD
Termination Threshold
Enable Threshold
(Internal Active Pull-up)
PP
amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.
= 1.25 V) right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified
2
2
PRELIMINARY TECHNICAL DATA
COREFB,BAD
Symbol
= 1.0 V at V
I
I
I
V
V
V
V
V
V
t
I
V
V
V
V
I
V
t
PWRGD,MSK
DACS
CC
CCUVLO
CCSD
SS
VID0..4
V
CCH
CCL
CCHYS
SDTH
COREFBH
PWRGD
SSENDWN
SSENUP
SSTERM
VID0..4
DAC
DAC
3
/V
7
DAC
6
VID
1
= 1.25 V setting) but gets into the CoreGood-window
( T
V
C
DAC
SD = L, 3.0 V
SD = H
V
V
V
0.9 V < V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VID 0..4 = L
See VID Code Table 1
0.850 V < V
0.600 V < V
SS
A
V
CC
CC
SS
COREFB
COREFB
COREFB
COREFB
COREFB
COREFB
CC
SS
SS
REG
RAMP
SS
SS
RAMP
SS
= 47 nF, R
( V
Conditions
DAC
= 0 V
= 0.5 V
floating
ramping down
ramping up
ramping up
ramping up, V
ramping down,
=
25 °C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, V
DACOUT
= 1.25 V,
–2–
DACOUT
= V
= V
3.3 V
= 0.5 V, C
= V
= 0.8 V
ramping up
ramping down
ramping up
ramping down
DAC
COREFB
COREFB
), V
settles within ±1% of its steady state value.
DACOUT
PWRGD
DAC
DAC
REG
< 1.675 V
DACOUT
= 680
< 1.750 V
< 0.825 V
= V
= 1.27 V
= 1.27 V
VCC
DAC
SS
CS–
= 0 V
= 10 nF
= V
to 1.2 V, R
3.6 V
VID
= 1.25 V, R
Min
2.65
50
1.12 V
1.10 V
0.88 V
0.86 V
0.95 V
0
1.75
0.600
–1.0
–8.5
CLAMP
COREFB,BAD
= 5.1 k to VCC, HYSSET, BSHIFT,
OUT
DAC
DAC
DAC
DAC
CC
= 100 k , C
7
10
V
100
–
0.5
80
150
2.00
V
90
3.5
Typ
16
= 1.0 V at V
CC
CC
/2
/2
Max
15
425
2.9
1.14 V
1.12 V
0.90 V
0.88 V
V
0.8
200
2.25
1.750
+1.0
+8.5
OUT
CC
VID
= 10 pF,
= 1.25 V setting) to
DAC
DAC
DAC
DAC
COREFB
mA
V
V
mV
V
V
V
V
V
V
V
mV
mV
V
V
V
%
mV
Units
REV. PrD
A
A
s
A
A
A
s
=