NCP1597AMNTWG ONSEMI [ON Semiconductor], NCP1597AMNTWG Datasheet - Page 12

• Manufacturer Part Number: NCP1597AMNTWG
• Description: 1 MHz, 2.0 A Synchronous Buck Regulator
• Manufacturer: ONSEMI [ON Semiconductor]

maximum ambient temperature. Calculate the power lost in
the NCP1597A using the following equations:
The conduction loss in the top switch is:
Where:
DI
The power lost due to switching the internal power high side
MOSFET is:
t
MOSFET measured at SW node.
The power dissipated in the top switch is:
Where:
DI
The switching loss for the low side MOSFET can be
ignored.
The power lost due to the quiescent current (I
is:
I
Calculate the temperature rise of the die using the following
equation:
r
Q
I
P
P
and t
RMS_LSFET
PP
PP
is the switching quiescent current of the NCP1597A.
Q
TOTAL
1. High side MOSFET
2. Low side MOSFET
+ V
is the peak−to−peak inductor current ripple.
is the peak−to−peak inductor current ripple.
f
are the rise and fall times of the internal power
+ P
in
I
RMS_FET
P
@ I
P
P
HSON
+
HSSW
LSON
Q
HSON
+ I
+ I
+
+
) P
I
out
2
V
RMS_LSFET
HSSW
RMS_HSFET
in
2
@ I
)
I
out
out
DI
) P
@ t
2
12
PP
)
2
2
LSON
r
2
@ R
DI
) t
12
R
PP
@ ( 1 * D )
DS(on)LS
f
) P
DS(on)HS
2
@ f
Q
SW
Q
) of the device
D
(eq. 10)
(eq. 12)
(eq. 13)
(eq. 14)
(eq. 11)
(eq. 8)
(eq. 9)
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12
1.7°C/W. T
junction
case−to−ambient thermal resistance is dependent on how
well heat can be transferred from the PC board to the air.
Solder the underside−exposed pad to a large copper GND
plane. If the die temperature reaches the thermal shutdown
threshold the NCP1597A shut down and does not restart
again until the die temperature cools by 30°C.
Layout Consideration
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For 1.0MHz
switching frequency, switch rise and fall times are typically
in few nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path must be
kept as short as possible. Shortening the current path will
also reduce the parasitic trace inductance of approximately
25 nH/inch. At switch off, this parasitic inductance
produces a flyback spike across the NCP1597A switch.
When operating at higher currents and input voltages, with
poor layout, this spike can generate voltages across the
NCP1597A that may exceed its absolute maximum rating.
A ground plane should always be used under the switcher
circuitry to prevent interplane coupling and overall noise.
from the switch node. The ground for these components
should be separated from the switch current path. Failure to
do so will result in poor stability or subharmonic like
oscillation.
resistance. Reducing the thermal resistance from ground pin
and exposed pad onto the board will reduce die temperature
and increase the power capability of the NCP1597A. This is
achieved by providing as much copper area as possible
around the exposed pad. Adding multiple thermal vias under
and around this pad to an internal ground plane will also
help. Similar treatment to the inductor pads will reduce any
additional heating effects.
T
q
As with all high frequency switchers, when considering
The FB component should be kept as far away as possible
Board layout also has a significant effect on thermal
J
JC
+ T
is the junction−to−case thermal resistance equal to
C
) P
temperature,
C
is the temperature of the case and TJ is the
TOTAL
@ q
JC
or
die
temperature.
(eq. 15)
The