AT17LV010-10DP-E ATMEL [ATMEL Corporation], AT17LV010-10DP-E Datasheet - Page 8

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AT17LV010-10DP-E

Manufacturer Part Number
AT17LV010-10DP-E
Description
Space FPGA Configuration EEPROM
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
AC Characteristics
AC Characteristics when
Cascading
8
A717LV010-10DP
V
Notes:
V
Notes:
Symbol
T
T
T
T
T
T
T
T
T
T
F
Symbol
T
T
T
T
F
CC
CC
OE
OH
OCK
OCE
OOE
CE
CAC
DF
LC
HC
SCE
HCE
HOE
MAX
CDF
MAX
(2)
(1)
(1)
= 3.3V ± 0.3V
(1)
= 3.3V ± 0.3V
(2)
(1)
(1)
(1)
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV
1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV
from steady-state active levels.
from steady-state active levels.
Description
OE to Data Delay
CE to Data Delay
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
CLK High Time
CE Setup Time to CLK
(to guarantee proper counting)
CE Hold Time from CLK
(to guarantee proper counting)
OE High Time (guarantees counter is reset)
Maximum Clock Frequency
Description
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay
Maximum Clock Frequency
Min
Min
25
25
35
25
0
0
Military
Military
Max
Max
50
55
40
40
10
55
60
60
50
10
4265B–AERO–06/04
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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