AT17F040 ATMEL [ATMEL Corporation], AT17F040 Datasheet - Page 5

• Manufacturer Part Number: AT17F040
• Description: FPGA CONFIGURATION FLASH MEMORY
• Manufacturer: ATMEL [ATMEL Corporation]

5. Pin Description
Table 5-1.
5.1
5.2
5.3
3039I–CNFG–2/05
Name
DATA
CLK
PAGE_EN
PAGESEL0
PAGESEL1
RESET/
CE
GND
CEO
A2
READY
SER_EN
V
CC
DATA
CLK
PAGE_EN
OE
(1)
Pin Description
(1)
I/O
I/O
(2)
O
O
–
–
I
I
I
I
I
I
I
I
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
Input used to enable page download mode. When PAGE_EN is high the configuration download
address space is partitioned into 4 equal pages. This gives users the ability to easily store and
retrieve multiple configuration bitstreams from a single configuration device. This input works in
conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.
When SER_EN is Low (ISP mode) this pin has no effect.
Notes:
LAP
8
1
2
–
–
–
3
4
5
6
–
7
8
1. This pin has an internal 20 K pull-up resistor.
2. This pin has an internal 30 K pull-down resistor.
AT17F040
PLCC
20
16
11
10
14
15
17
20
2
4
7
6
8
20 PLCC
(Virtex)
10
11
13
15
18
20
1
3
–
–
–
8
LAP
–
8
1
2
–
–
3
4
5
6
–
7
8
PLCC
20
16
11
10
14
15
17
20
2
4
7
6
8
AT17F080
AT17F040/080
PLCC
44
20
25
19
21
24
27
29
41
44
2
5
1
TQFP
44
40
43
39
14
19
13
15
18
21
23
35
38
5