E28F016XS20 INTEL [Intel Corporation], E28F016XS20 Datasheet - Page 13

• Manufacturer Part Number: E28F016XS20
• Description: 16-MBIT (1 MBIT x 16, 2 MBIT x 8) SYNCHRONOUS FLASH MEMORY
• Manufacturer: INTEL [Intel Corporation]

2.1
CLK
ADV#
RY/BY#
WP#
BYTE#
3/5#
V
V
PP
CC
Symbol
Lead Descriptions
OUTPUT
SUPPLY
SUPPLY
DRAIN
INPUT
INPUT
INPUT
INPUT
INPUT
OPEN
Type
(until publication date)
INTEL CONFIDENTIAL
CLOCK: Provides the fundamental timing and internal operating frequency.
CLK latches input addresses in conjunction with ADV#, times out the desired
output SFI Configuration as a function of the CLK period, and synchronizes
device outputs. CLK can be slowed or stopped with no loss of data or
synchronization. CLK is ignored during program operations.
ADDRESS VALID: Indicates that a valid address is present on the address
inputs. ADV# low at the rising edge of CLK latches the address on the address
inputs into the flash memory and initiates a read access to the even or odd
bank depending on the state of A
READY/BUSY: Indicates status of the internal WSM. When low, it indicates
that the WSM is busy performing an operation. RY/BY# high indicates that the
WSM is ready for new operations, erase is suspended, or the device is in deep
power-down mode. This output is always active (i.e., not floated to tri-state off
when OE# or CE
WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit
for each block. When WP# is low, those locked blocks as reflected by the
Block-Lock Status bits (BSR.6), are protected from inadvertent data programs
or erases. When WP# is high, all blocks can be written or erased regardless of
the state of the lock-bits. The WP# input buffer is disabled when RP#
transitions low (deep power-down mode).
BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or
output on DQ
low byte. BYTE# high places the device in x16 mode, and turns off the A
buffer. Address A
3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V
operation. 3/5# low configures internal circuits for 5.0V operation.
Reading the array with 3/5# high in a 5.0V system could damage the device.
Reference the power-up and reset timings (Section 5.10) for 3/5# switching
delay to valid data.
PROGRAM/ERASE POWER SUPPLY (12.0V ± 0.6V, 5.0V ± 0.5V) :
For erasing memory array blocks or writing words/bytes into the flash array.
V
0.6V option maximizes program/erase performance.
Successful completion of program and erase attempts is inhibited with V
or below 1.5V. Program and erase attempts with V
between 5.5V and 11.4V, and above 12.6V produce spurious results and
should not be attempted.
DEVICE POWER SUPPLY (3.3V ± 5%, 5.0V ± 5%):
To switch 3.3V to 5.0V (or vice versa), first ramp V
power to the new V
PP
= 5.0V ± 0.5V eliminates the need for a 12.0V converter, while the 12.0V ±
(Continued)
4/15/97 9:41 AM
0–7
, and DQ
0
1
#, CE
then becomes the lowest order address.
CC
voltage. Do not leave any power pins floating.
1
# are high).
8–15
9053204.DOC
Name and Function
float. Address A
1
. ADV# is ignored during program operations.
NOTE:
0
28F016XS FLASH MEMORY
selects between the high and
PP
CC
between 1.5V and 4.5V,
down to GND, and then
PP
0
input
at
13