27C256-25/L MICROCHIP [Microchip Technology], 27C256-25/L Datasheet - Page 6

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27C256-25/L

Manufacturer Part Number
27C256-25/L
Description
256K (32K x 8) Low-Voltage CMOS EPROM
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
27LV256
1.3
The standby mode is defined when the CE pin is high
(V
able
1.4
This feature eliminates bus contention in multiple bus
microprocessor systems and the outputs go to a high
impedance when the following condition is true:
• The OE pin is high and program mode is not
1.5
The Express algorithm has been developed to improve
on the programming throughput times in a production
environment. Up to 10 100-microsecond pulses are
applied until the byte is verified. No over-programming
is required. A flowchart of the express algorithm is
shown in Figure 1.
Programming takes place when:
a)
b)
c)
d)
Since the erased state is “1” in the array, programming
of “0” is required. The address to be programmed is set
via pins A0-A14 and the data to be programmed is pre-
sented to pins O0-O7. When data and address are sta-
ble, a low-going pulse on the CE line programs that
location.
DS11020H-page 6
IH
defined.
) and a program mode is not defined. Output Dis-
V
V
the OE pin is high
the CE pin is low
CC
PP
Standby Mode
Output Enable
Programming Mode
is brought to the proper V
is brought to the proper voltage
H
level
1.6
After the array has been programmed it must be veri-
fied to ensure that all the bits have been correctly pro-
grammed. This mode is entered when all of the
following conditions are met:
a)
b)
c)
d)
1.7
When Programming multiple devices in parallel with
different data, only CE needs to be under separate con-
trol to each device. By pulsing the CE line low on a par-
ticular device, that device will be programmed, and all
other devices with CE held high will not be pro-
grammed with the data although address and data are
available on their input pins.
1.8
In this mode specific data is outputted which identifies
the manufacturer as Microchip Technology Inc. and
device type. This mode is entered when Pin A9 is
taken to V
must be at V
non-erasable bytes whose data appears on O0 through
O7.
Pin
Manufacturer
Device Type*
* Code subject to change.
Identity
V
V
the CE pin is high
the OE line is low
CC
PP
Verify
is at the proper V
Inhibit
Identity Mode
is at the proper level
H
(11.5V to 12.5V). The CE and OE lines
IL
. A0 is used to access any of the two
Input
V
A0
V
IH
IL
0
1
0
7
2004 Microchip Technology Inc.
H
O
0
0
6
level
O
1
0
5
O
0
0
4
Output
O
1
1
3
O
0
1
2
O
0
0
1
1
0
O
0
29
8C
H
e
x

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