HM6-6642-9 INTERSIL [Intersil Corporation], HM6-6642-9 Datasheet - Page 2

• Manufacturer Part Number: HM6-6642-9
• Description: 512 x 8 CMOS PROM
• Manufacturer: INTERSIL [Intersil Corporation]

Pinouts
Functional Diagram
A8
A7
A6
A5
A4
A3
A2
A1
A0
E
G2
G3
GND
G1
Q0
Q1
Q2
A7
A6
A5
A4
A3
A2
A1
A0
10
11
12
1
2
3
4
5
6
7
8
9
HM-6642 (SBDIP)
REGISTER
REGISTER
ADDRESS
ADDRESS
LATCHED
LATCHED
TOP VIEW
A
A
24
23
22
21
20
19
18
17
16
15
14
13
A
A
6
6
3
3
V
A8
G1
G2
G3
E
P
Q7
Q6
Q5
Q4
Q3
CC
DECODER
GATED
ROW
NC
A4
A3
A2
A1
A0
Q0
Q0
10
11
5
6
7
8
9
12
4
Q1
64
D
13
3
HM-6642 (CLCC)
8
Q2
14
2
TOP VIEW
8
8-BIT DATA LATCH
HM-6642
15
GATED COLUMN
1
Q3
8
DECODER
MATRIX
6-2
16
64 x 64
28
8
17
27
8
Q4
18
26
8
25
24
23
22
21
20
19
8
Q5
8
G2
G3
E
P
NC
Q7
Q6
Q6
ALL LINES POSITIVE LOGIC - ACTIVE HIGH
THREE STATE BUFFERS:
DATA LATCHES:
ADDRESS LATCHES AND GATED DECODERS:
P SHOULD BE HARDWIRED TO GND EXCEPT
Q7
NOTE: P should be hardwired to GND
NC
A0-A8
E
Q
V
G1, G2, G3 Output Enable
P (Note)
A HIGH
L HIGH
Q LATCHES ON RISING EDGE OF E
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF E
DURING PROGRAMMING
CC
PIN
except during programming.
PIN DESCRIPTION
No Connect
Address Inputs
Chip Enable
Data Output
Power (+5V)
Program Enable
Q = D
OUTPUT ACTIVE
DESCRIPTION