STK10C48-NF25 SIMTEK [Simtek Corporation], STK10C48-NF25 Datasheet - Page 3

• Manufacturer Part Number: STK10C48-NF25
• Manufacturer: SIMTEK [Simtek Corporation]

March 2006
SRAM READ CYCLES #1 & #2
Note f:
Note g: I/O state assumes E, G < V
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
SRAM READ CYCLE #2: E Controlled
DQ (DATA OUT)
DQ (DATA OUT)
NO.
10
11
1
2
3
4
5
6
7
8
9
ADDRESS
ADDRESS
W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
t
t
t
t
t
t
t
t
t
t
t
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
#1, #2
I
CC
G
E
f
g
g
h
h
SYMBOLS
e
d, e
t
t
t
t
t
t
t
t
t
t
t
ACS
RC
AA
OE
OH
LZ
HZ
OLZ
OHZ
PA
PS
Alt.
IL
, W > V
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
STANDBY
IH
t
ELICCH
t
, and NE ≥ V
ELQX
t
AXQX
10
t
6
GLQX
5
8
t
GLQV
PARAMETER
4
IH
; device is continuously selected.
t
f
AVAV
t
ELQV
2
ACTIVE
t
AVQV
1
3
t
AVAV
3
2
f, g
Document Control # ML0002 rev 0.2
DATA VALID
STK10C48-25
MIN
25
5
5
0
0
MAX
25
25
10
10
10
25
DATA VALID
STK10C48-35
MIN
35
5
5
0
0
(V
t
GHQZ
9
MAX
CC
t
35
35
15
13
13
35
EHQZ
7
t
EHICCL
= 5.0V
11
STK10C48-45
MIN
45
5
5
0
0
STK10C48
MAX
45
45
20
15
15
45
±
10%)
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns