AT45DB642D-CNU-SL954 ATMEL [ATMEL Corporation], AT45DB642D-CNU-SL954 Datasheet - Page 36

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AT45DB642D-CNU-SL954

Manufacturer Part Number
AT45DB642D-CNU-SL954
Description
64-megabit 2.7-volt Dual-interface DataFlash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

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21. AC Waveforms
21.1
21.2
Note:
36
Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 66 MHz)
Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 66 MHz)
To operate the device at 50 MHz in SPI mode, the combined CPU setup time and rise/fall time should be less than 2 ns.
AT45DB642D
SCK/CLK
SCK/CLK
Six different timing waveforms are shown below. Waveform 1 shows the SCK/CLK signal being
low when CS makes a high-to-low transition, and waveform 2 shows the SCK/CLK signal being
high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the
SCK/CLK signal is still low (SCK/CLK low time is specified as t
conform to RapidS serial interface but for frequencies up to 66 MHz. Waveforms 1 and 2 are
compatible with SPI Mode 0 and SPI Mode 3, respectively.
Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These
are similar to waveform 1 and waveform 2, except that output SO is not restricted to become
valid during the t
imum frequency = 66 MHz) of the RapidS serial case. Waveform 5 and waveform 6 are for 8-bit
Rapid8 interface over the full frequency range of operation (maximum frequency = 50 MHz).
CS
SO
SO
CS
SI
SI
HIGH IMPEDANCE
HIGH Z
t
CSS
t
SU
t
t
V
CSS
t
SU
WL
period. These timing waveforms are valid over the full frequency range (max-
VALID IN
t
WL
VALID IN
VALID OUT
t
WH
t
WH
t
V
t
HO
t
H
t
H
t
WL
VALID OUT
t
HO
t
CSH
t
CSH
HIGH IMPEDANCE
t
t
HIGH IMPEDANCE
t
DIS
t
CS
DIS
CS
WL
). Timing waveforms 1 and 2
3542H–DFLASH–4/08

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