S-93C46BD0I-I8T1G SII [Seiko Instruments Inc], S-93C46BD0I-I8T1G Datasheet - Page 17

• Manufacturer Part Number: S-93C46BD0I-I8T1G
• Description: 3-WIRE SERIAL E2PROM
• Manufacturer: SII [Seiko Instruments Inc]

Rev.7.0
CS
SK
DO
DI
4. 5 Erasing chip (ERAL)
_00
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then
input the ERAL instruction and an address following the start bit. Any address can be input. There is no
need to input data. The chips erase operation starts when CS goes low. If the clocks more than the
specified number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For
details of the clock pulse monitoring circuit, refer to “
Erroneous Instruction Recognition ”.
CS
SK
DO
DI
1
0
2
1
3
0
0
2
High-Z
Figure 18 Chip Erase Timing (S-93C56B, S-93C66B)
1
4
3
0
High-Z
Figure 17 Chip Erase Timing (S-93C46B)
0
5
1
4
Seiko Instruments Inc.
6
0
5
7
6
6Xs
8
7
4Xs
9
8
Function to Protect Against Write due to
10
9
t
CDS
11
t
CDS
3-WIRE SERIAL E
t
SV
t
SV
t
S-93C46B/56B/66B
PR
Verify
busy
t
PR
Verify
busy
ready
ready
2
Standby
PROM
High-Z
Standby
t
HZ1
High-Z
17
t
HZ1