AT45D041-JI ATMEL [ATMEL Corporation], AT45D041-JI Datasheet - Page 7

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AT45D041-JI

Manufacturer Part Number
AT45D041-JI
Description
4-Megabit 5-volt Only Serial DataFlash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
AC Waveforms
Two different timing diagrams are shown below. Waveform
1 shows the SCK signal being low when CS makes a high-
to-low transition, and Waveform 2 shows the SCK signal
being high when CS makes a high-to-low transition. Both
wavforms show valid timing diagrams. The setup and hold
Waveform 1 – Inactive Clock Polarity Low
Waveform 2 – Inactive Clock Polarity High
Command Sequence for Read/Write Operations (Except Status Register Read)
Notes:
1.
2.
3.
“r” designates bits reserved for larger densities.
It is recommended that “r” be a logical “0” for densities of 4M bit or smaller.
For densities larger than 4M bit, the “r” bits become the most significant Page Address bit for the appropriate density.
SCK
SCK
SO
SO
CS
CS
SI
SI
MSB
HIGH IMPEDANCE
HIGH Z
larger densities
tCSS
Reserved for
SI
r r r r X X X X
tSU
tV
tCSS
tSU
tWL
VALID IN
VALID IN
VALID OUT
tWH
CMD
Page Address
tWH
(PA10-PA0)
tHO
tV
tH
X X X X X X X X
tH
tWL
8 bits
VALID OUT
times for the SI signal are referenced to the low-to-high
transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI
Mode 0, and Waveform 2 shows timing that is compatible
with SPI Mode 3.
8 bits
tHO
(BA8-BA0/BFA8-BFA0)
Byte/Buffer Address
tCSH
X X X X X X X X
tCSH
8 bits
tCS
tCS
HIGH IMPEDANCE
HIGH IMPEDANCE
tDIS
tDIS
LSB
7

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