CY62256VNLL-70SNC CYPRESS [Cypress Semiconductor], CY62256VNLL-70SNC Datasheet

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CY62256VNLL-70SNC

Manufacturer Part Number
CY62256VNLL-70SNC
Description
256K (32K x 8) Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Cypress Semiconductor Corporation
Document #: 001-06512 Rev. *A
Features
Logic Block Diagram
• Temperature Ranges
• Speed: 70 ns
• Low voltage range: 2.7V–3.6V
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in standard Pb-free and non Pb-free 28-lead
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
(300-mil) narrow SOIC, 28-lead TSOP-I and 28-lead
Reverse TSOP-I packages
CE
WE
OE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
198 Champion Court
INPUTBUFFER
DECODER
COLUMN
32K x 8
ARRA Y
Functional Description
The CY62256VN family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and tri-state drivers.
These devices have an automatic power-down feature,
reducing the power consumption by over 99% when
deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
addressed by the address present on the address pins (A
through A
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
POWER
DOWN
0
through I/O
256K (32K x 8) Static RAM
14
San Jose
). Reading the device is accomplished by selecting
7
) is written into the memory location
,
CA 95134-1709
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
[1]
0
1
2
3
4
5
6
7
Revised August 3, 2006
CY62256VN
408-943-2600
0
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CY62256VNLL-70SNC Summary of contents

Page 1

... Functional Description The CY62256VN family is composed of two high-performance CMOS static RAM’s organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tri-state drivers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected ...

Page 2

... Product Portfolio Product Range CY62256VNLL Com’l CY62256VNLL Ind’l CY62256VNLL Automotive-A CY62256VNLL Automotive-E Pin Configurations Narrow SOIC Top View ...

Page 3

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................ –65° 150°C Ambient Temperature with Power Applied............................................ –55° 125°C Supply Voltage to Ground Potential (Pin 28 to ...

Page 4

Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT [5] Thermal Resistance Parameter Description Θ Thermal Resistance Still Air, soldered × 4.5 inch, JA (Junction to Ambient) two-layer printed circuit board Θ Thermal Resistance ...

Page 5

... L 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. ...

Page 6

Switching Waveforms [12, 13] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [13, 14] Read Cycle No ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT [10, 15, ...

Page 7

Switching Waveforms (continued) [10, 15, 16] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS DATA I/O NOTE 17 t HZWE Document #: 001-06512 Rev. ...

Page 8

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 1.2 1.0 0 25°C 0.6 A 0.4 0.2 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 2.0 1 25°C A ...

Page 9

... H L Data Out Data High-Z Ordering Information Speed (ns) Ordering Code 70 CY62256VNLL-70SNC CY62256VNLL-70SNXC CY62256VNLL-70ZC CY62256VNLL-70ZXC CY62256VNLL-70SNXI CY62256VNLL-70ZI CY62256VNLL-70ZXI CY62256VNLL-70ZRI CY62256VNLL-70ZRXI CY62256VNLL-70ZXA CY62256VNLL-70SNXE CY62256VNLL-70ZXE CY62256VNLL-70ZRXE Please contact your local Cypress sales representative for availability of other parts Document #: 001-06512 Rev. *A (continued) NORMALIZED I 1 ...

Page 10

Package Diagrams Document #: 001-06512 Rev. *A 28-lead (300-mil) SNC (Narrow Body) (51-85092) 28-lead TSOP 1 (8 × 13.4 mm) (51-85071) CY62256VN 51-85092-*B 51-85071-*G Page [+] Feedback ...

Page 11

Package Diagrams (continued) 28-lead Reverse TSOP 1 (8 × 13.4 mm) (51-85074) All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 001-06512 Rev. *A © Cypress Semiconductor Corporation, 2006. The information ...

Page 12

Document History Page Document Title: CY62256VN 256K (32K x 8) Static RAM Document Number: 001-06512 Orig. of REV. ECN NO. Issue Date Change ** 426504 See ECN *A 488954 See ECN Document #: 001-06512 Rev. *A Description of Change NXR ...

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