CY62256VNLL CYPRESS [Cypress Semiconductor], CY62256VNLL Datasheet

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CY62256VNLL

Manufacturer Part Number
CY62256VNLL
Description
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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256K (32K × 8) Static RAM
Features
.
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-06512 Rev. *D
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Temperature ranges
Speed: 70 ns
Low voltage range: 2.7 V to 3.6 V
Low active power and standby power
Easy memory expansion with CE and OE features
TTL compatible inputs and outputs
Automatic power down when deselected
CMOS for optimum speed and power
Available in standard Pb-free and non Pb-free 28-pin (300-mil)
narrow SOIC, 28-pin TSOP-I, and 28-pin reverse TSOP-I
packages
Commercial: 0 °C to +70 °C
Industrial: –40 °C to +85 °C
Automotive-A: –40 °C to +85 °C
Automotive-E: –40 °C to +125 °C
CE
WE
OE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
198 Champion Court
INPUTBUFFER
DECODER
COLUMN
32K x 8
ARRA Y
POWER
DOWN
Functional Description
The CY62256VN
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and tristate drivers.
These devices have an automatic power down feature, reducing
the power consumption by over 99% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
by the address present on the address pins (A
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
0
through I/O
256K (32K × 8) Static RAM
San Jose
7
[1]
) is written into the memory location addressed
family is composed of two high performance
,
CA 95134-1709
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
Revised January 4, 2011
CY62256VN
0
408-943-2600
through A
14
).
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CY62256VNLL Summary of contents

Page 1

... Functional Description The CY62256VN CMOS static RAM’s organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tristate drivers. These devices have an automatic power down feature, reducing the power consumption by over 99% when deselected. ...

Page 2

Contents Product Portfolio .............................................................. 3 Pin Configurations ........................................................... 3 Pin Definitions .................................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Data Retention Characteristics ....................................... 5 Switching Characteristics ................................................ ...

Page 3

... Product Portfolio Product Range CY62256VNLL Commercial CY62256VNLL Industrial CY62256VNLL Automotive-A CY62256VNLL Automotive-E Pin Configurations Narrow SOIC Top View ...

Page 4

Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage ...

Page 5

Capacitance [6] Parameter Description C Input capacitance IN C Output capacitance OUT Thermal Resistance [6] Parameter Description  Thermal resistance JA (junction to ambient)  Thermal resistance JC (junction to case OUTPUT 50 pF INCLUDING JIG AND ...

Page 6

... L 12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. ...

Page 7

... Address valid prior to or coincident with CE transition LOW. 17. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. ...

Page 8

... Notes 21. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. ...

Page 9

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 1.2 1.0 0 25C 0.6 A 0.4 0.2 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 2.0 1 25C A ...

Page 10

Typical DC and AC Characteristics TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25 25 20.0 15.0 10.0 5.0 0.0 0 200 400 600 CAPACITANCE (pF) Truth Table Inputs/Outputs H ...

Page 11

... Ordering Information Speed Ordering Code (ns) 70 CY62256VNLL-70ZXC CY62256VNLL-70SNXI CY62256VNLL-70ZXI CY62256VNLL-70ZRXI CY62256VNLL-70SNXE CY62256VNLL-70ZXE Contact your local Cypress sales representative for availability of other parts Ordering Code Definitions CY 62 256 XXX Document Number: 001-06512 Rev. *D Package Package Type Diagram 51-85071 28-pin TSOP I (Pb-free) ...

Page 12

Package Diagrams Figure 8. 28-pin (300-mil) SNC (Narrow Body), 51-85092 Figure 9. 28-pin TSOP 1 (8 × 13.4 mm), 51-85071 Document Number: 001-06512 Rev. *D CY62256VN 51-85092 *C 51-85071 *H Page [+] Feedback ...

Page 13

Figure 10. 28-pin Reverse TSOP 1 (8 × 13.4 mm), 51-85074 Document Number: 001-06512 Rev. *D CY62256VN 51-85074-*F Page [+] Feedback ...

Page 14

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