W25Q64DWSFIG WINBOND [Winbond], W25Q64DWSFIG Datasheet - Page 25

• Manufacturer Part Number: W25Q64DWSFIG
• Description: 1.8V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI
• Manufacturer: WINBOND [Winbond]

10.2.10 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2,
LB1, LB0, QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit
locations are read-only and will not be affected by the Write Status Register instruction. LB3-0 are non-
volatile OTP bits, once it is set to 1, it can not be cleared to 0. The Status Register bits are shown in
Figure 4a and 4b, and described in 10.1.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register instruction (Status Register bit WEL
must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction
code “01h”, and then writing the status register data byte as illustrated in figure 9.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must
have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).
However, SRP1 and LB3, LB2, LB1, LB0 can not be changed from “1” to “0” because of the OTP
protection for these bits. Upon power off or the execution of a “Reset (99h)” instruction, the volatile Status
Register bit values will be lost, and the non-volatile Status Register bit values will be restored.
To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or
sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be
executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP, QE and
SRP1 bits will be cleared to 0.
During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high, the
self-timed Write Status Register cycle will commence for a time duration of t
While the Write Status Register cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle
CLK
/CS
IO
IO
IO
IO
Figure 8b. Read Status Register Instruction (QPI Mode)
0
1
2
3
Mode 3
Mode 0
Instruction
05h or 35h
0
- 25 -
1
SR1 or SR2
4
5
6
7
2
out
0
1
2
3
3
SR1 or SR2
4
5
6
7
4
out
Publication Release Date: January 13, 2011
0
1
2
3
5
4
5
6
7
W
(See AC Characteristics).
Preliminary - Revision C
W25Q64DW