M24M01-S STMICROELECTRONICS [STMicroelectronics], M24M01-S Datasheet - Page 3

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M24M01-S

Manufacturer Part Number
M24M01-S
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con-
nected from Serial Clock (SCL) to V
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to V
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Figure 4. Maximum R
20
16
12
8
4
0
10
L
Value versus Bus Capacitance (C
C BUS (pF)
CC
100
fc = 400kHz
. (Figure 4
CC
. (Fig-
fc = 100kHz
Chip Enable (E1, E2)
These input signals are used to set the value that
is to be looked for on bits b3 and b2 of the 7-bit De-
vice Select Code. These inputs must be tied to
V
When unconnected, the Chip Enable (E1, E2) sig-
nals are internally read as V
11).
Write Control (WC)
This input signal is useful for protecting the entire
contents of the memory from inadvertent write op-
erations. Write operations are disabled to the en-
tire memory array when Write Control (WC) is
driven High. When unconnected, the signal is in-
ternally read as V
lowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
CC
or V
BUS
SS
) for an I
1000
, to establish the Device Select Code.
MASTER
V CC
IL
2
, and Write operations are al-
C Bus
SDA
SCL
IL
(see Tables 10 and
R L
C BUS
R L
M24M01
AI01665
C BUS
3/19

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