M95128-MN3TP/P STMICROELECTRONICS [STMicroelectronics], M95128-MN3TP/P Datasheet - Page 19

• Manufacturer Part Number: M95128-MN3TP/P
• Description: 128 Kbit serial SPI bus EEPROM with high speed clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M95128, M95128-W, M95128-R
The protection features of the device are summarized in
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of whether Write Protect (W) is driven high or low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●
●
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered:
●
●
The only way to exit the Hardware-protected mode (HPM) once entered is to pull Write
Protect (W) high.
If Write Protect (W) is permanently tied high, the Hardware-protected mode (HPM) can
never be activated, and only the Software-protected mode (SPM), using the Block protect
(BP1, BP0) bits in the Status Register, can be used.
Figure 8.
If Write Protect (W) is driven high, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the Write enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution.) As a consequence, all the data bytes in the memory area that are
software-protected (SPM) by the Block protect (BP1, BP0) bits in the Status Register,
are also hardware-protected against data modification.
by setting the Status register write disable (SRWD) bit after driving Write Protect (W)
low
or by driving Write Protect (W) low after setting the Status Register Write Disable
(SRWD) bit.
S
C
D
Q
Write Status Register (WRSR) sequence
0
1
High Impedance
Doc ID 5798 Rev 13
2
Instruction
3
4
5
6
7
MSB
7
8
6
9 10 11 12 13 14 15
5
Register In
4
Status
Table
3
2
2.
1
0
AI02282D
Instructions
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