AT49BV8192A-12CC ATMEL [ATMEL Corporation], AT49BV8192A-12CC Datasheet - Page 2

• Manufacturer Part Number: AT49BV8192A-12CC
• Description: 8-Megabit 1M x 8/ 512K x 16 CMOS Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

*Standard device is a NC. Please contact Atmel for VPP option.
The device is erased by executing the erase command
sequence; the device internally controls the erase opera-
tion. The memory is divided into four blocks for erase oper-
ations. There are two 4K word parameter block sections,
the boot block, and the main memory array block. The typi-
cal number of program and erase cycles is in excess of
10,000 cycles.
The optional 8K word boot block section includes a repro-
gramming lock out feature to provide data integrity. This
feature is enabled by a command sequence. Once the boot
block programming lockout feature is enabled, the data in
the boot block cannot be changed when input levels of 3.6
volts or less are used. The boot sector is designed to con-
tain user secure code.
2
A
B
C
D
E
F
CBGA Top View (Ball Down)
BYTE
GND
A13
A14
A15
A16
1
I/O14
I/O15
AT49BV008A(T)/8192A(T)
I/O7
A11
A10
A12
2
AT49BV8192A(T)
*NC/VPP
RESET
I/O13
I/O5
I/O6
WE
A8
A9
A15
A14
A13
A12
A11
A10
A18
A17
3
WE
NC
NC
NC
NC
AT49BV8192A(T) TSOP Top View
A9
A8
A7
A6
A5
A4
A3
A2
A1
*NC/VPP
I/O11
I/O12
RST
I/O4
NC
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VCC
A18
I/O2
I/O3
NC
NC
5
I/O10
A17
I/O8
I/O9
NC
A6
6
Type 1
I/O0
I/O1
CE
A7
A5
A3
7
GND
OE
A4
A2
A1
A0
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AT49BV008A(T) Standard Pin Definition
A16
BYTE
GND
I/O15 / A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
C
D
A
B
E
F
CBGA Top View (Ball Down)
GND
A13
A14
A15
A16
NC
1
A11
A10
A12
I/O7
A-1
NC
2
I/O5
I/O6
WE
NC
A8
A9
3
VPP
RST
I/O4
NC
NC
NC
4
VCC
A18
I/O2
I/O3
NC
NC
5
For the AT49BV8192A(T), the BYTE pin controls whether
the device data I/O pins operate in the byte or word config-
uration. If the BYTE pin is set at a logic “1” or left open, the
device is in word configuration, I/O0 - I/O15 are active and
controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte con-
figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.
An optional V
times. Please contact Atmel for more information.
A17
NC
NC
NC
NC
A6
6
I/O0
I/O1
CE
A7
A5
A3
7
GND
OE
RDY/BUSY
A4
A2
A1
A0
8
*NC/VPP
RESET
A16
A15
A14
A13
A12
A11
A18
WE
A9
A8
A7
A6
A5
A4
A3
A2
A1
PP
AT49BV008A(T) TSOP Top View
pin is available to improve program/erase
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AT49BV008A(T) Alternate Pin Definition
C
D
A
B
E
F
Type 1
CBGA Top View (Ball Down)
GND
A14
A15
A16
A17
NC
1
A12
A10
A13
A11
I/O7
NC
2
WE
I/O5
I/O6
NC
A8
A9
3
VPP
RST
I/O4
NC
NC
NC
4
VCC
I/O2
I/O3
A19
NC
NC
5
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A18
NC
NC
NC
NC
A6
6
A17
GND
NC
A-1
A10
I/O7
I/O6
I/O5
I/O4
VCC
VCC
NC
I/O3
I/O2
I/O1
I/O0
OE
GND
CE
A0
I/O0
I/O1
CE
A7
A5
A3
7
GND
OE
A4
A2
A1
A0
8