AT25320B ATMEL [ATMEL Corporation], AT25320B Datasheet - Page 10

• Manufacturer Part Number: AT25320B
• Description: SPI Serial EEPROMs 32K (4096 x 8) 64K (8192 x 8)
• Manufacturer: ATMEL [ATMEL Corporation]

3. Timing Diagrams
Figure 3-1.
10
SCK
SO
CS
SI
AT25320B/640B
V
V
V
V
V
V
V
V
OH
OL
IH
IH
IH
IL
IL
IL
t
CSS
Synchronous Data Timing (for Mode 0)
HI-Z
A write instruction requires the following sequence. After the CS line is pulled low to select the
device, the WRITE op-code is transmitted via the SI line followed by the byte address (A15
and the data (D7
is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time
immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a read status register
(RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle
has ended. Only the RDSR instruction is enabled during the write programming cycle.
The AT25320B/640B is capable of a 32-byte page write operation. After each byte of data is
received, the five low-order address bits are internally incremented by one; the high-order bits of
the address will remain constant. If more than 32 bytes of data are transmitted, the address
counter will roll over and the previously written data will be overwritten. The AT25320B/640B is
automatically returned to the write disable state at the completion of a write cycle.
NOTE: If the device is not write-enabled (WREN), the device will ignore the write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is required to
reinitiate the serial communication.
Table 2-6.
t
SU
Don’t Care Bits
Address
VALID IN
Address Key
A
N
–
D0) to be programmed (see
t
WH
t
H
t
WL
AT25320B
A
A
15
Table
11
t
V
–A
–A
12
0
2-6). Programming will start after the CS pin
t
HO
AT25640B
A
A
15
12
t
CSH
–A
–A
13
0
8535B–SEEPR–7/08
t
DIS
t
HI-Z
CS
–
A0)