AT88SA10HS_10 ATMEL [ATMEL Corporation], AT88SA10HS_10 Datasheet - Page 10

• Manufacturer Part Number: AT88SA10HS_10
• Description: Atmel CryptoAuthentication Host Security Chip
• Manufacturer: ATMEL [ATMEL Corporation]

4.2.
4.3.
4.4.
4.4.1. IO Timeout
10
IO Blocks
Commands are sent to the chip, and responses received from the chip, within a block
following way:
IO Flow
The general IO flow for the commands is as follows:
1. System sends Wake token
2. System sends Transmit flag
3. Receive 0x11 value from Atmel AT88SA10HS to verify proper wakeup synchronization.
4. System sends Command flag
5. System sends complete command block
6. System waits t
7. System sends Transmit flag. If command format is OK, the Atmel AT88SA10HS ignores this flag because the
8. System waits t
9. System sends Transmit flag
10. Receive output block from the Atmel AT88SA10HS, system checks CRC
11. If CRC from Atmel AT88SA10HS is incorrect, indication transmission error, system resends Transmit flag
12. System sends sleep flag to the Atmel AT88SA10HS
Where the command in question has a short execution delay the system should omit steps six, seven and eight
and replace this with a wait of duration t
Synchronization
Because the communications protocol is half duplex, there is the possibility that the system and the Atmel
AT88SA10HS will fall out of synchronization with each other. In order to speed recovery, AT88SA10HS
implements a timeout that forces the AT88SA10HS to sleep.
After a leading transition for any data token has been received, AT88SA10HS will expect the remaining bits of the
token to be properly received by the chip within the t
transmission of an illegal token (a low pulse exceeding t
t
The same timeout applies during the transmission of the command block. After the transmission of a legal
command flag, the IO Timeout circuitry is enabled until the last expected data bit is received. Note that the
timeout counter is reset after every legal token, so the total time to transmit the command may exceed the t
interval while the time between bits may not.
Atmel AT88SA10HS Host Authentication Chip
TIMEOUT
Byte
Number
0
1 to (N-2) Packet
N-1, N
computation engine is busy. If there was an error, the Atmel AT88SA10HS responds with an error code
interval.
Name
Count
Checksum
PARSE
EXEC
, Refer to Section 4.1.1
for the Atmel AT88SA10HS to check for command formation errors
Meaning
Number of bytes to be transferred to the chip in the block, including count, packet and checksum,
so this byte should always have a value of (N+1). The maximum size block is 39 and the
minimum size block is four. Values outside this range will cause unpredictable operation.
Command, parameters and data, or response. Refer to Section 4.1.3 & Section 4 for more details.
CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the initial
register value should be 0 and after the last bit of the count and packet have been transmitted the
internal CRC register should have a value that matches that in the block. The first byte transmitted
(N-1) is the least significant byte of the CRC value so the last byte of the block is the most
significant byte of the CRC.
PARSE
+ t
EXEC
.
TIMEOUT
ZLO
) will cause the chip to enter the sleep state after the
interval. Failure to send enough bits or the
that is constructed in the
8595F–SMEM–8/10
®
TIMEOUT