AT25080B ATMEL [ATMEL Corporation], AT25080B Datasheet - Page 8

• Manufacturer Part Number: AT25080B
• Description: SPI Serial EEPROMs 8K (1024 x 8) 16K (2048 x 8)
• Manufacturer: ATMEL [ATMEL Corporation]

8
AT25080B/160B [Preliminary]
Table 2-1.
WRITE ENABLE (WREN): The device will power up in the write disable state when V
applied. All programming instructions must therefore be preceded by a Write Enable instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable
instruction disables all programming modes. The WRDI instruction is independent of the status
of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to
the status register. The READY/BUSY and Write Enable status of the device can be determined
by the RDSR instruction. Similarly, the Block Write Protection Bits indicate the extent of protec-
tion employed. These bits are set by using the WRSR instruction.
Table 2-2.
Table 2-3.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080B/160B is divided into four array segments. One-quarter,
one-half, or all of the memory segments can be protected. Any of the data within any selected
segment will therefore be read only. The block write protection levels and corresponding status
register control bits are shown in
The three bits BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g., WREN, t
Instruction Name
WRSR
READ
WRITE
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4–6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
Bits 0–7 are “1”s during an internal write cycle.
WPEN
Bit 7
Instruction Set for the AT25080B/160B
Read Status Register Bit Definition
Status Register Format
Bit 6
X
Definition
Bit 0 = “0” (RDY) indicates the device is READY. Bit 0 = “1” indicates the write cycle
is in progress.
Bit 1= “0” indicates the device is not WRITE ENABLED. Bit 1 = “1” indicates the
device is write enabled.
See
See
See
Table 2-4 on page 9
Table 2-4 on page 9
Table 2-5 on page 9
0000 X011
0000 X010
Instruction Format
0000 X001
Bit 5
X
Table
Bit 4
2-4.
X
.
.
.
Bit 3
BP1
Operation
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WC
, RDSR).
Bit 2
BP0
WEN
Bit 1
5228B–SEEPR–7/08
Bit 0
RDY
CC
is