11LC010T-ECS16K MICROCHIP [Microchip Technology], 11LC010T-ECS16K Datasheet
11LC010T-ECS16K
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11LC010T-ECS16K Summary of contents
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... Kbit through 16 Kbit Serial Electrically Erasable PROMs. The devices are organized in blocks of x8-bit memory and support the patented** single I/O UNI/O Manchester encoding techniques, the clock and data are combined into a single, serial bit stream (SCIO), where the clock signal is extracted by the receiver to correctly decode the timing and value of each bit ...
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DEVICE SELECTION TABLE Density Part Number Organization V (bits) 11LC010 1K 128 x 8 11AA010 1K 128 x 8 11LC020 2K 256 x 8 11AA020 2K 256 x 8 11LC040 4K 512 x 8 11AA040 4K 512 x 8 ...
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ELECTRICAL CHARACTERISTICS (†) Absolute Maximum Ratings V .............................................................................................................................................................................6.5V CC SCIO w.r.t. V .....................................................................................................................................-0. Storage temperature ................................................................................................................................. -65°C to 150°C Ambient temperature under bias............................................................................................................... -40°C to 125°C ESD protection on all pins.......................................................................................................................................... 4 kV † NOTICE: Stresses ...
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TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Sym. Characteristic No Serial bus frequency BUS 2 T Bit period Input edge jitter tolerance IJIT 4 F Serial bus frequency drift DRIFT rate tolerance 5 F ...
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FIGURE 1-1: BUS TIMING – START HEADER 10 11 SCIO Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK bit NoSAK bit FIGURE 1-2: BUS TIMING – DATA 2 SCIO Data ‘0’ ...
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... Both master and slave can operate as transmitter or receiver, but the master device determines which mode is active. FIGURE 2-1: BLOCK DIAGRAM STATUS Register Memory X I/O Control Control Logic Logic Dec Current- ...
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BUS CHARACTERISTICS 3.1 Standby Pulse When the master has control of SCIO, a standby pulse can be generated by holding SCIO high for T this time, the 11XX will reset and return to Standby mode. Subsequently, a high-to-low transition ...
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Acknowledge An Acknowledge routine occurs after each byte is transmitted, including the start header. This routine consists of two bits. The first bit is transmitted by the master, and the second bit is transmitted by the slave. Note: ...
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Device Standby The 11XX features a low-power Standby mode during which the device is waiting to begin a new command. A high-to-low transition on SCIO will exit low-power mode and prepare the device for receiving the start header. Standby ...
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... Read data from memory array beginning at specified address 0x03 Read data from current location in memory array 0x06 Write data to memory array beginning at specified address 0x6C Set the write enable latch (enable write operations) 0x96 Reset the write enable latch (disable write operations) ...
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... Current Address Read (CRRD) Instruction The internal address counter featured on the 11XX maintains the address of the last memory array loca- tion accessed. The CRRD instruction allows the mas- ter to read data back beginning from this current location. Consequently, no word address is provided upon issuing this command ...
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Write Instruction Prior to any attempt to write data to the 11XX, the write enable latch must be set by issuing the instruction (see Section 4.4). Once the write enable latch is set, the user may pro- ceed ...
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Write Enable (WREN) and Write Disable (WRDI) Instructions The 11XX contains a write enable latch. See Table 6-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be com- pleted internally. The WREN ...
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Read Status Register (RDSR) Instruction The RDSR instruction provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows ...
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Write Status Register (WRSR) Instruction The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four ...
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... Immediately after the NoMAK bit has been transmitted by the master, the internal write cycle is initiated, during which time all words of the memory array are written to ‘0xFF’. FIGURE 4-9: SET ALL COMMAND SEQUENCE Standby Pulse ...
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DATA PROTECTION The following protection has been implemented to prevent inadvertent writes to the array: • The Write Enable Latch (WEL) is reset on power- up • A Write Enable ( WREN ) instruction must be issued to set ...
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PIN DESCRIPTIONS The descriptions of the pins are listed in Table 7-1. TABLE 7-1: PIN FUNCTION TABLE Name 3-pin SOT-23 3-pin TO-92 SCIO — — 7.1 Serial ...
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PACKAGING INFORMATION 8.1 Package Marking Information 8-Lead PDIP XXXXXXXX T/XXXNNN 8-Lead PDIP Package Marking (Pb-Free) Device Line 1 Marking 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 Note Temperature Grade (I, E) Legend: XX...X Customer-specific information Y Year code ...
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... DS22067H-page 20 Example: 11AA160I e SN 0828 3 1L7 NNN Device 11AA010T 11LC010 11AA020T 11LC020 11AA040T 11LC040 11AA080T 11LC080 11AA160T 11LC160 11AA161T 11LC161 Preliminary Line 1 Marking 11LC010T 11LC020T 11LC040T 11LC080T 11LC160T 11LC161T ) e 3 2010 Microchip Technology Inc. ...
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MSOP (150 mil) 8-Lead MSOP Package Marking (Pb-Free) Device Line 1 Marking 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 Note Temperature Grade (I, E) Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year ...
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TDFN 8-Lead 2x3 TDFN Package Marking (Pb-Free) Device I-Temp Marking 11AA010 D11 11AA020 D21 11AA040 D31 11AA080 D41 11AA160 D51 11AA161 D5D Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code ...
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SOT-23 XXNN 3-Lead SOT-23 Package Marking (Pb-Free) Device I-Temp Marking 11AA010 B1NN 11AA020 B2NN 11AA040 B3NN 11AA080 B4NN 11AA160 B5NN 11AA161 B0NN Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 ...
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TO-92 XXXXXX T/XXXX YWW NNN 3-Lead TO-92 Package Marking (Pb-Free) Device Line 1 Marking 11AA010 11AA020 11AA040 11AA080 11AA160 11AA161 Note Temperature Grade (I, E) Legend: XX...X Customer-specific information Y Year code (last digit of calendar ...
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Chip Scale 4-Lead Chip Scale Package Marking (Pb-Free) Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) ...
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N NOTE DS22067H-page Preliminary c 2010 Microchip Technology Inc. ...
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N NOTE 2010 Microchip Technology Inc. 11AAXXX/11LCXXX φ Preliminary α c β DS22067H-page 27 ...
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DS22067H-page 28 Preliminary 2010 Microchip Technology Inc. ...
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D N NOTE 2010 Microchip Technology Inc. 11AAXXX/11LCXXX Preliminary φ L DS22067H-page 29 ...
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DS22067H-page 30 Preliminary 2010 Microchip Technology Inc. ...
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Microchip Technology Inc. 11AAXXX/11LCXXX Preliminary DS22067H-page 31 ...
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DS22067H-page Preliminary D 2010 Microchip Technology Inc. ...
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2010 Microchip Technology Inc. 11AAXXX/11LCXXX Preliminary φ L DS22067H-page 33 ...
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22067H-page 34 Preliminary 2010 Microchip Technology Inc. ...
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc. 11AAXXX/11LCXXX Preliminary DS22067H-page 35 ...
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22067H-page 36 Preliminary 2010 Microchip Technology Inc. ...
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APPENDIX A: REVISION HISTORY Revision A (10/07) Original release of this document. Revision B (01/08) Revised SOT-23 Package Type; Revised DFN package to TDFN; Section 3.3 (added new bullet item); Section 4.5 note; Table 7-1. Revision C (03/08) Removed patent ...
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NOTES: DS22067H-page 38 Preliminary 2010 Microchip Technology Inc. ...
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THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web ...
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READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which ...
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PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office PART NO Device Device Tape & Reel Temperature Address Device: 11AA01 = 1 Kbit, 1.8V UNI/O ...
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NOTES: DS22067H-page 42 Preliminary 2010 Microchip Technology Inc. ...
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... India. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC ® devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary ...
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W ORLDWIDE AMERICAS ASIA/PACIFIC Corporate Office Asia Pacific Office 2355 West Chandler Blvd. Suites 3707-14, 37th Floor Chandler, AZ 85224-6199 Tower 6, The Gateway Tel: 480-792-7200 Harbour City, Kowloon Fax: 480-792-7277 Hong Kong Technical Support: Tel: 852-2401-1200 http://support.microchip.com Fax: 852-2401-3431 ...