24AA512 MICROCHIP [Microchip Technology], 24AA512 Datasheet - Page 5

• Manufacturer Part Number: 24AA512
• Description: 512K I2C CMOS Serial EEPROM
• Manufacturer: MICROCHIP [Microchip Technology]

2.0
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
The A0, A1 and A2 inputs are used by the 24XX512 for
multiple device operations. The logic levels on these
inputs are compared with the corresponding bits in the
slave address. The chip is selected if the compare is
true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. If these
pins are left unconnected, the inputs will be pulled
down internally to V
high, the internal pull-down circuitry is disabled.
In most applications, the chip address inputs A0, A1,
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable logic device,
the chip address pins must be driven to logic ‘0’ or logic
‘1’ before normal device operation can proceed.
2.2
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
 2004 Microchip Technology Inc.
Name
(NC)
(NC)
SDA
SCL
V
V
WP
A0
A1
A2
CC
SS
PIN DESCRIPTIONS
A0, A1 and A2 Chip Address
Inputs
Serial Data (SDA)
CC
PIN FUNCTION TABLE
(typical 10 k
SS
PDIP
. If they are tied to V
—
—
1
2
3
4
5
6
7
8
for 100 kHz, 2 k
SOIC
—
—
1
2
3
4
5
6
7
8
CC
or driven
24AA512/24LC512/24FC512
10, 11, 12
14-lead
TSSOP
3, 4, 5
13
14
for
1
2
6
7
8
9
2.3
This input is used to synchronize the data transfer from
and to the device.
2.4
This pin can be connected to either V
Internal pull-down circuitry on this pin will keep the
device in the unprotected state if left floating, however,
floating this pin is not recommended for most
applications. If tied to V
enabled (read/write the entire memory 0000-FFFF).
If tied to V
operations are not affected.
3.0
The 24XX512 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
serial clock (SCL), controls the bus access and
24XX512 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the
controlled by a master device which generates the
generates the Start and Stop conditions, while the
master device determines which mode is activated.
DFN
—
—
1
2
3
4
5
6
7
8
Serial Clock (SCL)
Write-Protect (WP)
FUNCTIONAL DESCRIPTION
CC
User Configured Chip Select
User Configured Chip Select
Not Connected
User Configured Chip Select
Ground
Serial Data
Serial Clock
Not Connected
Write-Protect Input
+1.8V to 5.5V (24AA512)
+2.5V to 5.5V (24LC512)
+2.5V to 5.5V (24FC512)
, write operations are inhibited. Read
SS
, normal memory operation is
Function
DS21754E-page 5
SS
or V
CC
.