93AA56A MICROCHIP [Microchip Technology], 93AA56A Datasheet - Page 6
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93AA56A
Manufacturer Part Number
93AA56A
Description
2K Microwire Compatible Serial EEPROM
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.93AA56A.pdf
(24 pages)
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93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C
2.4
The ERASE instruction forces all data bits of the speci-
fied address to the logical ‘1’ state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed program-
ming cycle, except on ‘93C’ devices where the rising
edge of CLK before the last address bit initiates the
write cycle.
FIGURE 2-1:
FIGURE 2-2:
DS21794B-page 6
CLK
CLK
DO
DO
CS
DI
CS
DI
ERASE
HIGH-Z
HIGH-Z
1
1
ERASE TIMING FOR 93AA AND 93LC DEVICES
ERASE TIMING FOR 93C DEVICES
1
1
1
1
A
A
N
N
A
A
N
N
-1
-1
A
A
N
N
-2
-2
•••
•••
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
is still in progress. DO at logical ‘1’ indicates that the
register at the specified address has been erased and
the device is ready for another instruction.
A0
A0
Note:
T
T
CSL
CSL
CSL
). DO at logical ‘0’ indicates that programming
Issuing a START bit and then taking CS low
will clear the READY/BUSY status from
DO.
T
WC
T
T
T
SV
WC
SV
CHECK STATUS
CHECK STATUS
BUSY
BUSY
2003 Microchip Technology Inc.
READY
READY
HIGH-Z
HIGH-Z
T
T
CZ
CZ