24AA01T MICROCHIP [Microchip Technology], 24AA01T Datasheet - Page 9

• Manufacturer Part Number: 24AA01T
• Description: 1K I2C Serial EEPROM
• Manufacturer: MICROCHIP [Microchip Technology]

7.0
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘
of read operations: current address read, random read
and sequential read.
7.1
The 24XX01 contains an address counter that
maintains the address of the last word accessed,
internally incremented by ‘
access (either a read or write operation) was to
address
would access data from address
the slave address with R/W bit set to ‘
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a Stop condition and the 24XX01
discontinues transmission (Figure 7-1).
7.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX01 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the inter-
nal address pointer is set. The master then issues the
control byte again, but with the R/W bit set to a ‘
24XX01 will then issue an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer but does generate a Stop condition and the
24XX01 discontinues transmission (Figure 7-2).
FIGURE 7-1:
 2003 Microchip Technology Inc.
READ OPERATION
Current Address Read
Random Read
n
, the next current address read operation
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
CURRENT ADDRESS READ
1
’. There are three basic types
1
’. Therefore, if the previous
n + 1
S
T
A
R
T
S
. Upon receipt of
1
’, the 24XX01
CONTROL
1
’. The
BYTE
7.3
Sequential reads are initiated in the same way as a
random read, except that once the 24XX01 transmits
the first data byte, the master issues an acknowledge
(as opposed to a Stop condition in a random read). This
directs the 24XX01 to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24XX01 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
7.4
The 24XX01 employs a V
which disables the internal erase/write logic if the V
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
A
C
K
24AA01/24LC01B
Sequential Read
Noise Protection
DATA (n)
CC
threshold detector circuit
O
N
C
A
K
P
O
S
T
P
DS21711C-page 9
CC