MAX8900A MAXIM [Maxim Integrated Products], MAX8900A Datasheet - Page 32
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MAX8900A
Manufacturer Part Number
MAX8900A
Description
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
1.MAX8900A.pdf
(35 pages)
list of guidelines in addition to Application Note 1891:
Wafer-Level Packaging (WLP) and Its Applications
maxim-ic.com/ucsp) to layout the MAX8900_ PCB.
The guidelines at the top are the most critical:
1) When the step-down converter’s high-side MOSFET
2) When the step-down converter is increasing the cur-
3) When the step-down converter is decreasing the
4) The LX node voltage switches between INBP and
5) In Figure 14, the CS node is connected to the second
1.2A Switch-Mode Li+ Chargers with ±22V Input
Rating and JEITA Battery Temperature Monitoring
32
turns on, C
INBP. Because of this high di/dt current pulse, place
C
ance in the PCB trace.
rent in the inductor, the high-side MOSFET is on and
current flows in the following path: from C
INBP >> out of LX >> through the inductor >> into CS
>> out of BAT >> through C
through the ground plane. This current loop should
be kept small and the electrical length from the posi-
tive terminal of C
minimize parasitic impedance. The electrical length
from the negative terminal of C
terminal of C
sitic impedance. Keep all sensitive signals such as
feedback nodes or audio lines outside of this current
loop with as much isolation as your design allows.
inductor current, the low-side MOSFET is on and
the current flows in the following path: out of LX >>
through the inductor >> into CS >> out of BAT >>
through C
current loop should be kept small and the electrical
length from the negative terminal of C
should be short to minimize parasitic impedance.
Keep all sensitive signals such as feedback nodes or
audio lines outside of this current loop with as much
isolation as your design allows.
PGND during the operation of the step-down con-
verter. Minimize the stray capacitance on the LX node
to maintain good efficiency. Also, keep all sensitive
signals such as feedback nodes or audio lines away
from LX with as much isolation as your design allows.
layer of metal with vias. Use low-impedance vias that
are capable of handling 1.5A of current. Also, keep
the routing inductor current path on layer 2 just under-
neath the inductor current path on layer 1 to minimize
impedance.
INBP
close to INBP to minimize the parasitic imped-
BAT
INBP
INBP
>> into PGND >> out of LX again. This
delivers a high di/dt current pulse to
INBP
should be short to minimize para-
to INBP should be kept short to
BAT
BAT
and back to C
to the negative
BAT
INBP
to PGND
(www.
INBP
into
6) Both C
7) Each of the MAX8900_ bumps has approximately the
In Figure 14, many of the top layer bump pads are con-
nected together in top metal. When connecting bumps
together with top layer metal, the solder mask must
define the pads from 180Fm to 210Fm as shown in
Figure 15. When using solder mask defined pads, please
double check the solder mask openings on the PCB
Gerber files before ordering boards as some PCB lay-
out tools have configuration settings that automatically
oversize solder mask openings. Also, explain in the PCB
fabrication notes that the solder mask is not to be modi-
fied. Occasionally, optimization tools are used at the
PCB fabrication house that modify solder masks. Layouts
that do not use solder mask defined pads are possible.
When using these layouts, adhere to the recommenda-
tions A through G above.
Figure 14. Power PCB Layout Example
MAX8900_’s MOSFET drivers. These components
should be placed as shown in Figure 14 to minimize
parasitic impedance.
same ability to remove heat from the die. Connect as
much metal as possible to each bump to minimize the
B
Management section for more information on B
JA
associated with the MAX8900_. See the Thermal
BST
and C
PVL
deliver current pulses for the
JA
.