LMC6082AMN NSC [National Semiconductor], LMC6082AMN Datasheet - Page 8

• Manufacturer Part Number: LMC6082AMN
• Description: Precision CMOS Dual Operational Amplifier
• Manufacturer: NSC [National Semiconductor]

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CAPACITIVE LOAD TOLERANCE
All rail-to-rail output swing operational amplifiers have volt-
age gain in the output stage. A compensation capacitor is
normally included in this integrator stage. The frequency lo-
cation of the dominant pole is affected by the resistive load
on the amplifier. Capacitive load driving capability can be op-
timized by using an appropriate resistive load in parallel with
the capacitive load (see typical curves).
Direct capacitive loading will reduce the phase margin of
many op-amps. A pole in the feedback loop is created by the
combination of the op-amp’s output impedance and the ca-
pacitive load. This pole induces phase lag at the unity-gain
crossover frequency of the amplifier resulting in either an os-
cillatory or underdamped pulse response. With a few exter-
nal components, op amps can easily indirectly drive capaci-
tive loads, as shown in Figure 2 .
In the circuit of Figure 2 , R1 and C1 serve to counteract the
loss of phase margin by feeding the high frequency compo-
nent of the output signal back to the amplifier’s inverting in-
put, thereby preserving phase margin in the overall feedback
loop.
Capacitive load driving capability is enhanced by using a
pull up resistor to V
conducting 500 µA or more will significantly improve capaci-
tive load responses. The value of the pull up resistor must be
determined based on the current sinking capability of the
FIGURE 2. LMC6082 Noninverting Gain of 10 Amplifier,
FIGURE 1. Cancelling the Effect of Input Capacitance
Compensated to Handle Capacitive Loads
+
Figure 3 . Typically a pull up resistor
(Continued)
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8
amplifier with respect to the desired output swing. Open loop
gain of the amplifier can also be affected by the pull up resis-
tor (see Electrical Characteristics).
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC6082, typically less
than 10 fA, it is essential to have an excellent layout. Fortu-
nately, the techniques of obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear accept-
ably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6082’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs, as in Fig-
ure 4 . To have a significant effect, guard rings should be
placed on both the top and bottom of the PC board. This PC
foil must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of the input. This
would cause a 100 times degradation from the LMC6082’s
actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 10
cause only 0.05 pA of leakage current. See Figure 5 for typi-
cal connections of guard rings for standard op-amp
configurations.
FIGURE 3. Compensating for Large Capacitive Loads
FIGURE 4. Example of Guard Ring in P.C. Board
with a Pull Up Resistor
Layout
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12
, which is nor-
11
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would