CS8421_06 CIRRUS [Cirrus Logic], CS8421_06 Datasheet
CS8421_06
Related parts for CS8421_06
CS8421_06 Summary of contents
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Asynchronous Sample Rate Converter Features ! 175 dB Dynamic Range ! –140 dB THD Programming Required ! No External Master Clock Required ! Supports Sample Rates up to 211 kHz ! Input/Output Sample Rate Ratios ...
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General Description The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter. Digital audio inputs and outputs can be 32, 24, 20, or 16-bits. Input and output data can be completely asynchro- nous, synchronous to an external data ...
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TABLE OF CONTENTS 1. PIN DESCRIPTIONS ............................................................................................................................ 6 1.1 TSSOP Pin Descriptions ................................................................................................................ 6 1.2 QFN Pin Descriptions ..................................................................................................................... 8 2. CHARACTERISTICS AND SPECIFICATIONS ................................................................................... 10 SPECIFIED OPERATING CONDITIONS ............................................................................................ 10 ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 10 PERFORMANCE SPECIFICATIONS.................................................................................................. 11 DIGITAL ...
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LIST OF FIGURES Figure 1. Non-TDM Slave Mode Timing..................................................................................................... 14 Figure 2. TDM Slave Mode Timing ............................................................................................................ 14 Figure 3. Non-TDM Master Mode Timing................................................................................................... 14 Figure 4. TDM Master Mode Timing .......................................................................................................... 14 Figure 5. Typical Connection Diagram, No External ...
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Figure 53. Linearity Error -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz ........................................ 31 Figure 54. Linearity Error -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz ................................... 31 Figure 55. Linearity Error ...
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PIN DESCRIPTIONS 1.1 TSSOP PIN DESCRIPTIONS XTO XTI VD GND RST BYPASS ILRCK ISCLK SDIN MCLK_OUT CS8421 SRC_UNLOCK ...
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Pin Name # XTO 1 Crystal Out (Output) - Crystal output for Master clock. See Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See XTI 2 on page 21 Digital Power (Input) - Digital ...
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QFN PIN DESCRIPTIONS VD GND RST BYPASS ILRCK Thermal Pad 4 Top-Down View 20-pin QFN Package CS8421 VL 15 GND 14 13 MS_SEL 12 ...
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Pin Name # VD 1 Digital Power (Input) - Digital core power supply. Typically +2.5 V. GND 2 Ground (Input) - Ground for I/O and core logic. Reset (Input) - When RST is low, the CS8421 enters a low-power mode ...
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CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25°C.) A SPECIFIED OPERATING CONDITIONS (GND = ...
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PERFORMANCE SPECIFICATIONS (XTI/XTO = 27 MHz; Input signal = 1.000 kHz, 0 dBFS, Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 32-Bits, unless otherwise stated.) Parameter Resolution Sample Rate with XTI = 27.000 MHz Sample Rate with ...
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DIGITAL FILTER CHARACTERISTICS Parameter Passband (Upsampling or Downsampling) Passband Ripple Stopband Stopband Attenuation Group Delay 3. The equation for the group delay through the sample-rate converter is (56.581 / Fsi) + (55.658 / Fso). For example, if the input sample ...
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DIGITAL INPUT CHARACTERISTICS Parameters Input Leakage Current Input Capacitance Input Hysteresis DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to 0 V.) Parameters High-Level Output Voltage, except MCLK_OUT and SDOUT (I Low-Level Output Voltage, except MCLK_OUT and ...
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Parameters Master Mode (Note 9) I/OSCLK Frequency (non-TDM) OSCLK Frequency (TDM) I/OLRCK Duty Cycle I/OSCLK Duty Cycle I/OSCLK Falling Edge to I/OLRCK Edge OSCLK Falling Edge to OLRCK Edge (TDM) OSCLK Falling Edge to SDOUT Output Valid SDIN/TDM_IN Setup Time ...
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TYPICAL CONNECTION DIAGRAMS 0.1 µF Serial Audio Source * 1 kΩ ** Hardware Control Settings Figure 5. Typical Connection Diagram, No External Master Clock * When no external master clock is supplied to the part, both input and output ...
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Serial Audio Source * Hardware Control Settings Figure 6. Typical Connection Diagram, Master and Slave Modes * The connection (VL or GND) and value of these three resistors determines the mode of operation for the input and output ...
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APPLICATIONS The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter. The digital audio data is input and output through configurable 3-wire serial ports. The digital audio input/output ports offer Left-Justified, Right-Justified, and I²S serial audio formats. ...
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I/OLRCK Channel A I/OSCLK SDIN SDOUT I/OLRCK Channel A I/OSCLK SDIN SDOUT Figure 8. Serial Audio Interface Format - Left-Justified I/OLRCK Channel A I/OSCLK SDIN SDOUT MSB Extended Figure 9. Serial Audio Interface Format ...
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MS_SEL pin 1.0 kΩ ± GND 1.96 kΩ ± GND 4.02 kΩ ± GND 8.06 kΩ ± GND 16.2 kΩ ± GND 1.0 kΩ ± 1.96 kΩ ...
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Sample Rate Converter (SRC) Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very high rate and then downsample to the outgoing rate. The internal data path is 32-bits wide even if a ...
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Muting The SDOUT pin is set to all zero output (full mute) immediately after the RST pin is set high. When the output from the SRC becomes valid, though the SRC may not have reached full performance, SDOUT is ...
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Clocking In order to ensure proper operation of the CS8421, the clock or crystal attached to XTI must simultaneous- ly satisfy the requirements of LRCK for both the input and output as follows: • If the input is set ...
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Time Division Multiplexing (TDM) Mode TDM Mode allows several CS8421 to be serially connected together allowing their corresponding SDOUT data to be multiplexed onto one line for input into a DSP or other TDM-capable multichannel device. The CS8421 can ...
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Output LRCK Clock SCLK Source CS8421 1 OLRCK OSCLK TDM_IN SDOUT ILRCK ISCLK Slave SDIN OLRCK OSCLK SDOUT OLRCK OSCLK SDOUT PCM Source 1 PCM Source 2 Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave) CS8421 1 OLRCK ...
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PERFORMANCE PLOTS +0 -20 -40 -60 - -100 F S -120 -140 -160 -180 -200 5k 10k Hz Figure 15. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz +0 -20 -40 -60 ...
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B -100 F S -120 -140 -160 -180 -200 5k 10k Hz Figure 21. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 192 kHz:48 kHz -60 -80 -100 d -120 B F ...
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-140 -160 -180 -200 5k 10k Hz Figure 27. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 96 kHz:48 kHz -60 -80 -100 d -120 -140 -160 ...
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B -100 F S -120 -140 -160 -180 -200 20k 40k Hz Figure 33. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Tone, 192 kHz:192 kHz +0 -20 -40 -60 - ...
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B -135 F S -137.5 -140 -142.5 -145 -147.5 -150 50k 75k 100k 125k Hz Figure 39. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 48 kHz -120 -122.5 ...
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B -135 F S -137.5 -140 -142.5 -145 -147.5 -150 50k 75k 100k 125k Hz Figure 45. Dynamic Range vs. Output Sample Rate dBFS 1 kHz Tone, Fsi = 96 kHz ...
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B - -80 -90 -100 -110 -120 -130 -140 -140 -120 -100 -80 -60 dBFS Figure 51. Linearity Error -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz ...
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B -145 F S -150 -155 -160 -165 -170 -175 -180 -140 -120 -100 -80 -60 dBFS Figure 57. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:44.1 kHz -110 -115 -120 ...
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B -145 F S -150 -155 -160 -165 -170 -175 -180 0 2.5k 5k 7.5k 10k Hz Figure 63. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:44.1 kHz -110 -115 -120 -125 ...
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PACKAGE DIMENSIONS 20L TSSOP (4.4 MM BODY) PACKAGE DRAWING TOP VIEW INCHES DIM MIN 0.002 0.004 A2 0.03346 0.0354 b 0.00748 0.0096 D 0.252 0.256 E 0.248 0.2519 E1 0.169 0.1732 ...
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QFN (5 × BODY) PACKAGE DRAWING D Pin #1 Corner Top View INCHES DIM MIN 0.0000 b 0.0091 0.0110 D 0.1969 BSC D2 0.1201 0.1220 E 0.1969 BSC E2 0.1202 0.1221 e 0.0256 BSC ...
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ORDERING INFORMATION ORDERING INFORMATION Product Description 32-bit Asynchronous Sample Rate CS8421 Converter CDB8421 Evaluation Board for CS8421 8. REVISION HISTORY Release A1 Initial Advance Release -Updated “Features” on page -Updated “Sample Rate with other XTI clocks” on page -Updated ...
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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in ...
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CS8421 DS641F1 ...