CS8405A-IZ CIRRUS [Cirrus Logic], CS8405A-IZ Datasheet - Page 26

• Manufacturer Part Number: CS8405A-IZ
• Description: 96 KHZ DIGITAL AUDIO INTERFACE TRANSMITTER
• Manufacturer: CIRRUS [Cirrus Logic]

10. HARDWARE MODE
The CS8405A has a hardware mode that allows the
use of the device without a microcontroller. Hard-
ware mode is selected by connecting the H/S pin to
VL+. The flexibility of the CS8405A is necessarily
limited in hardware mode. Various pins change
function as described in the hardware mode pin de-
scription section.
The hardware mode data flow is shown in
Figure 10. Audio data is input through the serial au-
dio input port and routed to the AES3 transmitter.
10.1 Channel Status, User and Validity
The transmitted channel status, user and validity
data can be input in two methods, determined by
the state of the CEN pin. Mode A is selected when
the CEN pin is low. In mode A, the user bit data and
the validity bit are input through the U and V pins,
clocked by both edges of ILRCK. The channel sta-
tus data is derived from the state of the COPY/C,
ORIG, EMPH, and AUDIO pins. Table 2 shows
how the COPY/C and ORIG pins map to channel
status bits. In consumer mode, the transmitted cat-
egory code is set to Sample Rate Converter
(0101100).
26
Data
ILRCK
ISCLK
SDIN
Power supply pins and the reset pin are omitted from this diagram.
Please refer to the Typical Connection Diagram for hook-up details.
APMS
Serial
Audio
Input
SFMT1 SFMT0
Figure 10. Hardware Mode
COPY/C ORIG EMPH AUDIO TCBL
VL +
H/S
Mode B is selected when the CEN pin is high. In
mode B, the channel status, user data bits and the
validity bit are input serially through the COPY/C,
U and V pins. Data is clocked into these pins at
both edges of ILRCK. Figure 7 shows the timing
requirements.
The channel status block pin (TCBL) may be an in-
put or an output, determined by the state of the
TCBLD pin.
10.2 Serial Audio Port Formats
The serial audio input port data format is selected
as shown in Table 3, and may be set to master or
slave by the state of the APMS input pin. Table 4
describes the equivalent software mode, bit settings
for each of the available formats. Timing diagrams
are shown in Figure 6.
COPY/C
Table 2. Hardware Mode COPY/C and ORIG pin
C, U, V Data Buffer
0
0
1
1
ORIG
0
1
0
1
Output
Clock
Source
AES3
Encoder
& Tx
PRO=0, COPY=0, L=0 copyright
PRO=0, COPY=0, L=1 copyright,
pre-recorded
PRO=0, COPY=1, L=0
non-copyright
PRO=1
OMCK
TCBLD
functions
TXP
TXN
CEN
U
V
Function
CS8405A
DS469PP4