CLC1603IST6X CADEKA [Cadeka Microcircuits LLC.], CLC1603IST6X Datasheet - Page 17

• Manufacturer Part Number: CLC1603IST6X
• Description: Single and Triple, 1.1mA, 200MHz Amplifiers
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

Data Sheet
In order to determine P
needs to be subtracted from the total power delivered by
the supplies.
P
Supply power is calculated by the standard power equa-
tion.
P
V
Power delivered to a purely resistive load is:
P
The effective load resistor (Rload
the effect of the feedback network. For instance,
Rload
R
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, P
P
Quiescent power can be derived from the specified I
ues along with known supply voltage, V
can be calculated as above with the desired signal ampli-
tudes using:
(V
( I
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
P
Assuming the load is referenced in the middle of the power
rails or V
Figure 8 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8 and 14 lead
SOIC packages.
©2007-2008 CADEKA Microcircuits LLC
D
supply
load
D
DYNAMIC
supply
L
LOAD
LOAD
= P
|| (R
= P
= ((V
eff
supply
Quiescent
)
)
= V
= V
D
RMS
f
RMS
in figure 3 would be calculated as:
supply
+ R
can be found from
= (V
LOAD
supply
S+
= V
= ( V
- P
g
)
- V
/2.
S+
load
)
+ P
PEAK
RMS
× I
S-
LOAD
- V
Dynamic
2
RMS supply
)/Rload
/ √2
LOAD
)
RMS
D
, the power dissipated in the load
)
RMS
- P
/ Rload
eff
Load
× ( I
eff
eff
LOAD
) will need to include
)
Supply
RMS
. Load power
S
val-
Better thermal ratings can be achieved by maximizing PC
board metallization at the package pins. However, be care-
ful of stray capacitance on the input pins.
In addition, increased airflow across the package can also
help to reduce the effective Ө
In the event the outputs are momentarily shorted to a low
impedance path, internal circuitry and output metallization
are set to limit and handle up to 65mA of output current.
However, extended duration under these conditions may
not guarantee that the maximum junction temperature
(+150°C) is not exceeded.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
2.5
1.5
0.5
2
1
0
-40
SOIC-14
Figure 8. Maximum Power Derating
-20
SOT23-6
Ambient Temperature (°C)
0
20
JA
of the package.
SOIC-16
40
www.cadeka.com
60
80
17