CLC408AJE NSC [National Semiconductor], CLC408AJE Datasheet - Page 8

• Manufacturer Part Number: CLC408AJE
• Description: Comlinear CLC408 High-Speed, Low-Power Line Driver
• Manufacturer: NSC [National Semiconductor]

http://www.national.com
Unity gain applications are limited by the Common-Mode
Input Range. At greater non-inverting gains, the Output
Voltage Range becomes the limiting factor.
gain applications are limited by the Output Voltage
Range (and by the previous amplifier’s ability to drive
R
the input currents injected at the inverting input pin of
the op amp needs to be:
Output Voltage Range (see the DC Gain (transimpedance)
sub-section for details).
The equivalent output load needs to be large enough
so that the output current can produce the required out-
put voltage swing. See the DC Design (output loading)
sub-section for details.
Dynamic Range (noise)
The output noise defines the lower end of the CLC408’s
useful dynamic range. Reduce the value of resistors in
the circuit to reduce noise.
See the App Note Noise Design of CFB Op Amp
Circuits for more details. Our SPICE models support noise
simulations.
Dynamic Range (distortion)
The distortion plots in the Typical Performance
Characteristics section show distortion as a function
of load resistance, frequency, and output amplitude.
Distortion places an upper limit on the CLC408’s
dynamic range.
The CLC408’s output stage combines a voltage buffer
with a complementary common emitter current source.
The interaction between the buffer and the current
source produces a small amount of crossover distortion.
This distortion mechanism dominates at low output swing
and low resistance loads. To avoid this type of distortion,
use the CLC408 at high output swing.
Realized output distortion is highly dependent upon the
external circuit. Some of the common external circuit
choices that can improve distortion are:
Printed Circuit Board Layout
High frequency op amp performance is strongly dependent
on proper layout, proper resistive termination and
adequate power supply decoupling. The most important
layout points to follow are:
g
). For transimpedance gain applications, the sum of
Short and equal return paths from the load to
the supplies
De-coupling capacitors of the correct value
Higher load resistance
Use a ground plane
Bypass power supply pins with:
I
in
V
R
max
f
, where V
max
Inverting
is the
8
Evaluation Board
Separate evaluation boards are available for proto-typing
and measurements. Additional information is available in
the evaluation board literature.
SPICE Models
SPICE models provide a means to evaluate op amp
designs. Free SPICE models are available that:
The readme file that accompanies the models lists the
released models, and provides a list of modeled
parameters.
SPICE Models for Comlinear’s Op Amps contains
schematics and detailed information.
The circuit shown in the Typical Application schematic
on the front page operates as a full duplex cable driver
which allows simultaneous transmission and reception of
signals on one transmission line. The circuit on either
side of the transmission line uses the CLC408 as a cable
driver, and the CLC426 as a receiver. V
version of Vi
R
set the DC gain of the CLC426, which is used in a differ-
ence mode. R
CLC408 is shown in a unity gain configuration because it
consumes the least power of any gain, for a given load.
For proper operation we need R
The receiver output voltages are:
where A is the attenuation of the cable, Z
output impedance of the CLC408 (see the Closed-Loop
Output Resistance plot), and
m1
V
outA(B)
is used to match the transmission line. R
Minimize trace and lead lengths for components
between the inverting and output pins
Remove ground plane underneath the amplifier
package and 0.1” (3mm) from all input/output pads
For prototyping, use flush-mount printed circuit
board pins; never use high profile DIP sockets .
Support Berkeley SPICE 2G and its many
derivatives
Reproduce typical DC, AC, Transient, and
Noise performance
Support room temperature simulations
CLC408 Applications
nA
monolithic capacitors of about 0.1 F place
tantalum capacitors of about 6.8 F for
less than 0.1” (3mm) from the pin
large signal current swings or improved
power supply noise rejection;
we recommend a minimum of 2.2 F
for any circuit
V
t2
inA(B)
, while V
The
provides good CMRR and DC offset. The
A
application
oB
V
is an attenuated version of V
inB(A)
2
|
Z
f2
1
o(408)
= R
R
R
note
g2
f2
g2
oA
(j )
.
is an attenuated
o(408)
|
Z
<< R
o(408)
Simulation
R
f2
(j ) is the
m1
m1
and R
(j )
.
inB
g2
.