CLC1006 CADEKA [Cadeka Microcircuits LLC.], CLC1006 Datasheet - Page 13

• Manufacturer Part Number: CLC1006
• Description: Single, 500MHz Voltage Feedback Amplifier
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

Data Sheet
Driving Capacitive Loads
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
R
stability and settling performance. Refer to Figure 4.
Table 1 provides the recommended R
tive loads. The recommended R
peaking in the frequency response. The Frequency Re-
sponse vs. C
the CLC1006.
For a given load capacitance, adjust R
tradeoff between settling time and bandwidth. In general,
©2007-2008 CADEKA Microcircuits LLC
S
Input
, between the amplifier and the load to help improve
2.5
1.5
0.5
C
2
1
0
1000
L
100
500
-40
20
50
(pF)
R
g
Figure 3. Maximum Power Derating
Figure 4. Addition of R
+
Table 1: Recommended R
-
L
-20
plots, on page 7, illustrates the response of
SOT23-5
R
f
R
Capacitive Loads
Ambient Temperature (°C)
3.3
S
0
20
15
11
6
(Ω)
R
s
SOIC-8
20
C
L
S
-3dB BW (MHz)
S
values result in <=1dB
40
for Driving
R
S
L
S
300
210
150
for various capaci-
68
55
vs. C
S
Output
to optimize the
60
L
80
reducing R
ditional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when ei-
ther one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLC1006 will typically recover in less
than 25ns from an overdrive condition. Figure 5 shows the
CLC1006 in an overdriven condition.
Layout Considerations
General layout and supply bypassing play major roles
in high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
-1
-2
-3
3
2
1
0
0
Input
20
S
will increase bandwidth at the expense of ad-
40
Figure 5. Overdrive Recovery
60
Output
80
Time (ns)
100
120
140
160
V
G = 5
www.cadeka.com
IN
= 2.5V
180
pp
200
5
4
3
2
1
0
-1
-2
-3
-4
-5
13