EL5126 INTERSIL [Intersil Corporation], EL5126 Datasheet - Page 5

• Manufacturer Part Number: EL5126
• Description: 8-Channel TFT-LCD Reference Voltage Generator
• Manufacturer: INTERSIL [Intersil Corporation]

Typical Performance Curves
General Description
The EL5126 provides a versatile method of providing the
reference voltages that are used in setting the transfer
characteristics of LCD display panels. The V/T
(Voltage/Transmission) curve of the LCD panel requires that
a correction is applied to make it linear; however, if the panel
is to be used in more than one application, the final curve
may differ for different applications. By using the EL5126,
the V/T curve can be changed to optimize its characteristics
according to the required application of the display product.
Each of the eight reference voltage outputs can be set with a
10-bit resolution. These outputs can be driven to within
50mV of the power rails of the EL5126. As all of the output
buffers are identical, it is also possible to use the EL5126 for
applications other than LCDs where multiple voltage
references are required that can be set to 10 bit accuracy.
FIGURE 9. SMALL SIGNAL RESPONSE (FALLING FROM
200mV TO 0V)
OUTPUT
M=400µs/DIV
5
FIGURE 11. POWER DISSIPATION vs AMBIENT TEMPERATURE
SCLK
SDA
(Continued)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
(SINGLE LAYER) TEST BOARD
758mW
JEDEC JESD51-3 AND SEMI G42-88
25
AMBIENT TEMPERATURE (°C)
EL5126
50
75
Digital Interface
The EL5126 uses a simple two-wire I
program the outputs. The bus line SCLK is the clock signal
line and bus SDA is the data information signal line. The
EL5126 can support the clock rate up to 400kHz. External
pull up resistor is required for each bus line. The typical
value for these two pull up resistor is about 1kΩ.
START AND STOP CONDITION
The Start condition is a high to low transition on the SDA line
while SCLK is high. The Stop condition is a low to high
transition on the SDA line while SCLK is high. The start and
stop conditions are always generated by the master. The
bus is considered to be busy after the start condition and to
be free again a certain time after the stop condition. The two
bus lines must be high when the buses are not in use. The
I
2
85
FIGURE 10. POWER DISSIPATION vs AMBIENT
C Timing Diagram 2 shows the format.
100
125
2.5
1.5
0.5
TEMPERATURE
3
2
1
0
0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - LPP EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
150
2.857W
25
AMBIENT TEMPERATURE (°C)
50
75
85
2
C digital interface to
100
125
150