EL5287CY INTERSIL [Intersil Corporation], EL5287CY Datasheet - Page 7

• Manufacturer Part Number: EL5287CY
• Description: Window 4ns High-Speed Comparator
• Manufacturer: INTERSIL [Intersil Corporation]

Applications Information
Power Supplies and Circuit Layout
The EL5287 comparator operates with single and dual
supply with 5V to 12V between V
side of the comparator is supplied by a single supply from
2.7V to 5V. The rail to rail output swing enables direct
connection of the comparator to both CMOS and TTL logic
circuits. As with many high speed devices, the supplies must
be well bypassed. Elantec recommends a 4.7µF tantalum in
parallel with a 0.1µF ceramic. These should be placed as
close as possible to the supply pins. Keep all leads short to
reduce stray capacitance and lead inductance. This will also
minimize unwanted parasitic feedback around the
comparator. The device should be soldered directly to the
PC board instead of using a socket. Use a PC board with a
good, unbroken low inductance ground plane. Good ground
Pin Descriptions
PIN NUMBER
10
1
2
3
4
5
6
7
8
9
PIN NAME
VREFH
VREFL
LATCH
OUTH
OUTL
GND
VSD
VS+
VS-
IN
7
Positive supply voltage
Upper voltage reference
Input
Lower voltage reference
Negative supply voltage
Digital ground
Low output
Latch
High output
Digital supply voltage
S
+ and V
S
-. The output
FUNCTION
EL5287
plane construction techniques enhance stability of the
comparators.
Input Voltage Considerations
The EL5287’s input range is specified from 0.1V below V
to 2.25V below V
the output still responds correctly to a small differential input
signal. The differential input stage is a pair of PNP
transistors, therefore, the input bias current flows out of the
device. When either input signal falls below the negative
input voltage limit, the parasitic PN junction formed by the
substrate and the base of the PNP will turn on, resulting in a
significant increase of input bias current. If one of the inputs
goes above the positive input voltage limit, the output will still
maintain the correct logic level as long as the other input
stays within the input range. However, the propagation delay
will increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differential
(Reference Circuit 1)
(Reference Circuit 1)
(Reference Circuit 2)
VREF
LATCH
S
+. The criterion for the input limit is that
EQUIVALENT CIRCUIT
V
S
+
V
V
SD
S
-
V
SD
V
Circuit 1
Circuit 2
Circuit 3
S
+
V
S
-
V
SD
OUT
V
V
S
S
IN
+
-
S
-