OPA682N BURR-BROWN [Burr-Brown Corporation], OPA682N Datasheet - Page 19

• Manufacturer Part Number: OPA682N
• Description: Wideband, Fixed Gain BUFFER AMPLIFIER With Disable
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

FIGURE 9. Disable/Enable Glitch.
The transition edge rate (dV/dt) of the DIS control line will
influence this glitch. For the plot of Figure 9, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 1V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
V
transition logic is used, a 2k
logic gate and the DIS input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
DIS pin while still ensuring an adequate logic level swing.
THERMAL ANALYSIS
Due to the high output power capability of the OPA682,
heatsinking or forced airflow may be required under extreme
operating conditions. Maximum desired junction tempera-
ture will set the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed 175 C.
Operating junction temperature (T
The total internal power dissipation (P
quiescent power (P
the output stage (P
power is simply the specified no-load supply current times
the total supply voltage across the part. P
the required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is fixed at
a voltage equal to 1/2 either supply voltage (for equal bipolar
supplies). Under this condition P
includes feedback network loading.
Note that it is the power in the output stage and not in the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
OPA682N (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85 C and driving a grounded 20
DIS
P
Maximum T
D
–20
–40
= 10V • 7.2mA + 5
pin from a higher speed logic line. If extremely fast
40
20
0
J
= +85 C + (0.39W • 150 C/W) = 144 C
DQ
DL
V
Output Voltage
) and additional power dissipated in
DIS
) to deliver load power. Quiescent
(0V Input)
2
0.2V
/(4 • (20
Time (20ns/div)
series resistor between the
DL
J
) is given by T
= V
load to +2.5V DC:
|| 800 )) = 392mW
S
2
/(4 • R
4.8V
D
DL
) is the sum of
will depend on
A
L
) where R
+ P
J
using an
D
•
JA
L
.
19
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. Remember,
this is a worst-case internal power dissipation-use your
actual signal and load to compute P
internal dissipation will occur if the load requires current to
be forced into the output for positive output voltages or
sourced from the output for negative output voltages. This
puts a high current through a large internal voltage drop in
the output transistors. The Output Voltage and Current Limi-
tations plot shown in the Typical Performance Curves in-
clude a boundary for 1W maximum internal power dissipa-
tion under these conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA682 requires careful attention to board
layout parasitics and external component types. Recommen-
dations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the
output pin can cause instability: on the non-inverting input,
it can react with the source impedance to cause unintentional
bandlimiting. To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all of the
ground and power planes around those pins. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the power sup-
ply pins to high frequency 0.1 F decoupling capacitors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The power
supply connections (on pins 4 and 7) should always be
decoupled with these capacitors. An optional supply
decoupling capacitor across the two power supplies (for
bipolar operation) will improve 2nd harmonic distortion
performance. Larger (2.2 F to 6.8 F) decoupling capaci-
tors, effective at lower frequency, should also be used on the
main supply pins. These may be placed somewhat farther
from the device and may be shared among several devices in
the same area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of
the OPA682. Any external resistors should be a very low
reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Metal-film and carbon composition,
axially-leaded resistors can also provide good high fre-
quency performance. Again, keep their leads and PC board
trace length as short as possible. Never use wirewound type
resistors in a high frequency application. All external com-
ponents should also be placed close to the package.
OPA682
DL
. The highest possible
®