ADL5811-EVALZ AD [Analog Devices], ADL5811-EVALZ Datasheet - Page 24

• Manufacturer Part Number: ADL5811-EVALZ
• Description: High IP3, 700 MHz to 2800 MHz, Double Balanced, Passive Mixer, IF Amplifier, and Wideband LO Amplifier
• Manufacturer: AD [Analog Devices]

ADL5811
REGISTER STRUCTURE
Figure 60 illustrates the register map of the ADL5811. The
ADL5811
control bits to 5. When set to 0, the ENBL bit, DB7, enables the
part. By setting this bit to 1, the mixer is powered down. The
RFB IN CAP DAC and RFB OUT CAP DAC bits are used to tune
the RF balun. In most cases, they are tuned together with the
higher settings, 7, tuning for the low frequencies, and with the
lower settings, 0, tuning for the high frequencies. There are
times where it becomes advantageous to tune the input and
output of the RF balun separately and that ability is provided.
Table 11. Optimum Settings
RF Frequency (MHz)
700
800
900
1000
1100
1200
1300
1400
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
2600
2700
2800
VGS2 VGS1 VGS0
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14
RESERVED
0
1
'
0
0
1
'
only uses Register 5. Because of this, set all of the
0
0
1
'
VGS2 VGS1 VGS0 LPF1 LPF0
LPF1 LPF0 LOW PASS FILTER SETTING
0
1
'
VGS
VGS SETTING
0
1
'
0
7
'
LO Frequency (MHz)
497
597
697
797
897
997
1097
1197
1297
1397
1497
1597
1697
1797
1897
1997
2097
2197
2297
2397
2497
2597
LPF
0
3
'
CDO2 CDO1 CDO0 RF BALUN OUTPUT TUNING
0
1
'
0
0
1
'
CDO2 DCDO1 CDO0
RFB OUT CAP DAC
0
1
'
Figure 60. ADL5811 Register Maps
DB13 DB12 DB11 DB10
Rev. 0 | Page 24 of 28
0
VGS
3
1
2
1
3
3
3
3
3
3
3
3
3
3
3
2
3
2
3
3
1
3
0
7
'
CDI2 CDI1 CDI0 RF BALUN INTPUT TUNING
0
1
'
CDI2
RFB IN CAP DAC
0
1
'
The LPF bits control the low-pass filter settings at the IF output.
The ability to tune the low-pass filter allows some trade-off
between gain, noise figure, and input IP3 with higher settings,
7, providing higher input IP3 at the cost of some gain and noise
figure, and lower settings, 0, providing higher gain and lower
NF at the cost of lower input IP3. The VGS bits control the VGS
settings of the mixer core and allow further tuning of the device.
Table 11 lists the optimum settings characterized for each
frequency band. All register bits default to 0.
CDI1
LPF
1
1
1
1
1
3
3
3
3
3
3
3
3
3
3
3
2
2
3
2
2
2
0
1
'
CDI0
DB9
RFB OUT CAP DAC
7
6
6
4
7
5
5
4
4
3
3
3
2
2
1
2
2
2
1
2
2
1
DB8
0
ENBL
MEN
DB7
7
EN
0
'
0
1
DB6
DEVICE DISABLED
DEVICE ENABLED
0
MAIN ENABLE
RESERVED
DB5
0
DB4
0
DB3
0
RFB IN CAP DAC
7
6
6
4
7
5
5
4
4
3
3
3
2
2
1
2
2
2
1
2
2
1
C3(1) C2(0) C1(1)
DB2
CONTROL BITS
DB1
DB0