ADL5523_09 AD [Analog Devices], ADL5523_09 Datasheet
ADL5523_09
Related parts for ADL5523_09
ADL5523_09 Summary of contents
Page 1
FEATURES Operation from 400 MHz to 4000 MHz Noise figure of 0 900 MHz Requires few external components Integrated active bias control circuit Integrated dc blocking capacitors Adjustable bias for low power applications Single-supply operation from 3 V ...
Page 2
ADL5523 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Specifications .......................................................................... 3 DC Specifications ......................................................................... 4 De-Embedded S-Parameters, VPOS = ...
Page 3
SPECIFICATIONS AC SPECIFICATIONS T = 25° 1.3 kΩ; parameters include matching circuit, matched for optimal noise, unless otherwise noted. A Table 1. Parameter FREQUENCY = 900 MHz Gain (S21) vs. Frequency vs. Temperature 1 Noise Figure Output Third-Order ...
Page 4
ADL5523 DC SPECIFICATIONS Table 2. Parameter Conditions Supply Current vs. Temperature −40°C ≤ DE-EMBEDDED S-PARAMETERS, VPOS = RFIN = PORT 1, VPOS = PORT 2, RFOUT = PORT 3 Table 3. Frequency S11 ...
Page 5
ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage, VPOS RF Input Level RF Input Level (with 8 Ω Series Resistor on VPOS) Internal Power Dissipation θ (Junction to Air) JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Stresses ...
Page 6
ADL5523 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 VBIAS Internal DC Bias. This pin should be connected to VPOS through the R1 resistor. 2 RFIN RF Input. This is the input to ...
Page 7
TYPICAL PERFORMANCE CHARACTERISTICS 900 MHz, VPOS = 5 V Matched for optimal noise figure, external matching circuit included. 25 S21 S11 –5 –10 –15 S22 –20 –25 –30 –35 600 650 700 750 800 850 ...
Page 8
ADL5523 1950 MHZ, VPOS = 5 V Matched for optimal noise figure, external matching circuit included. 20 S21 S11 –5 –10 –15 –20 –25 S22 –30 –35 –40 1800 1850 1900 1950 2000 2050 FREQUENCY (MHz) ...
Page 9
MHz, VPOS = 5 V Matched for optimal noise figure, external matching circuit included. 20 S21 S11 –5 S22 –10 –15 –20 S12 –25 –30 2100 2200 2300 2400 2500 2600 FREQUENCY (MHz) Figure 15. ...
Page 10
ADL5523 3500 MHz, VPOS = 5 V Matched for optimal noise figure, external matching circuit included S11 –5 –10 S22 –15 –20 –25 2800 2900 3000 3100 3200 3300 FREQUENCY (MHz) Figure 21. Typical S-Parameters, Log ...
Page 11
MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included S11 –5 –10 S22 –15 –20 –25 –30 –35 600 650 700 750 800 850 900 950 1000 1050 ...
Page 12
ADL5523 1950 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included S11 –5 –10 –15 –20 –25 –30 S22 –35 1800 1850 1900 1950 2000 2050 FREQUENCY (MHz) Figure 33. ...
Page 13
MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included. 20 S21 S11 –5 S22 –10 –15 S12 –20 –25 –30 2100 2200 2300 2400 2500 2600 FREQUENCY (MHz) Figure 39. ...
Page 14
ADL5523 3500 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included. 15 S21 S11 –5 –10 –15 S22 –20 –25 2800 2900 3000 3100 3200 3300 FREQUENCY (MHz) Figure 45. Typical S-Parameters, ...
Page 15
DC CHARACTERISTICS VPOS = VPOS = –40 –30 –20 – TEMPERATURE (°C) Figure 51. Supply Current vs. Temperature and ...
Page 16
ADL5523 BASIC CONNECTIONS The basic connections for operating the ADL5523 are shown in Figure 52. Capacitor C5 provides the power supply decoupling. Inductor L1 (Coilcraft 0403HQ or 0402HP series) and Capacitor C1 (Murata High-Q GJM series or equivalent) provide the ...
Page 17
EVALUATION BOARD Figure 53 shows the schematic of the ADL5523 evaluation board. The board is powered by a single supply, and dc bias can be applied to the board through clip-on leads at VPOS and GND or through a 2-pin ...
Page 18
ADL5523 TUNING THE ADL5523 FOR OPTIMAL NOISE FIGURE The ADL5523 is a monolithic low noise amplifier (LNA × LFCSP. The evaluation board, as shipped from the factory, gives a noise figure of 0.9 dB ...
Page 19
TUNING THE LNA INPUT FOR OPTIMAL GAIN LNAs are generally tuned for either gain or noise optimization, or some trade-off between the two. One figure of merit of an LNA is how much trade-off must be made for one of ...
Page 20
ADL5523 S11 OF THE LNA WITH S22 MATCHED To determine the correct matching circuit for optimal noise, look at the results of S11 for the various frequencies at which S22 was tuned earlier in the Tuning S22 section. Once S11 ...
Page 21
OUTLINE DIMENSIONS PIN 1 INDICATOR 0.90 MAX 0.85 NOM SEATING PLANE ORDERING GUIDE Model Temperature Range 1 ADL5523ACPZ-R7 −40°C to +85°C 1 ADL5523-EVALZ RoHS Compliant Part. 3.25 0.60 MAX 3.00 SQ 2.75 0.60 MAX 2.95 2.75 SQ ...
Page 22
ADL5523 NOTES Rev Page ...
Page 23
NOTES Rev Page ADL5523 ...
Page 24
ADL5523 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06829-0-9/09(A) Rev Page ...