LT5554IUH-PBF LINER [Linear Technology], LT5554IUH-PBF Datasheet - Page 23
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LT5554IUH-PBF
Manufacturer Part Number
LT5554IUH-PBF
Description
Broadband Ultra Low Distortion 7-Bit Digitally Controlled VGA
Manufacturer
LINER [Linear Technology]
Datasheet
1.LT5554IUH-PBF.pdf
(32 pages)
Layout Considerations
Attention must be paid to the printed circuit board layout
to avoid output pin to input pin signal coupling (external
feedback). The evaluation board layout is a good example.
The exposed backside pad on the LT5554 package must be
soldered to PCB ground plane for thermal considerations.
Characterization Test Circuits
The LT5554’s typical performance data are on the test
circuits shown in Figures 16, 17 and 18 which are simpli-
fi ed schematics of the evaluation board schematic from
Figure 21.
APPLICATIONS INFORMATION
J1
50
V
V
CC
CCO
1, 3, 5, 7
0.1μF
= 5V
ETC1-1-13
= 5V
C4
MACOM
V
•
CC
1:1
T1
•
V
DEC
0.1μF
9
C8
Figure 16. Single-Ended Transformer Test Board (Simplifi ed Schematic)
11
ENB
13
PG0
C5
1μF
R20
10k
IN
IN
15
PG1
+
–
PG0
R
OUT
17
R21
PG2
R
50Ω
10k
400Ω
IN
= 50Ω
PG1
R
19
O
PG3
OUT
OUT
R22
10k
21
–
+
LT5554
PG2
PG4
400Ω
R
O
23
R23
10k
PG5
PG3
R
57.1Ω
25
68.1Ω
LOAD
PG6
R24
10k
R5
The transformer board from Figure 16 was used for char-
acterization as a function of R
The T2 transformer model and the matching resistors R5,
R6 values are given in Table 3. The T2 transformer total
matching resistance is R
LT5554 internal, and part on board R5 and R6).
Table 3. Transformer Board R
R
T2 (Mini-Circuits)
N
R
R5, R6 (Ω)
G
IL(T2) at
200MHz (dB)
PG4
OUT
LOAD
LOAD
P_BOARD
STROBE
27
R6
68.1Ω
R25
10k
(Ω)
Ratio
(Ω)
0.1μF
PG5
C3
(dB)
MATCHING
OUTPUT
0.1μF
R26
10k
V
C9
29
PG
PG6
0.1μF
C18
31
MODE
TC2-1T
57.1
68.1
13.2
–0.6
50
33, 35, 37, 38
2
TC2-1T
•
•
OUT
MATCH
2:1
T2
V
CCO
•
Options
4.7μF
OUT
C19
= R
. For each R
TC3-1T
J5, 40 PINS
SMT-TB
2, 4, ...40
–0.65
92.3
124
75
16
3
O
|| (R5 + R6) (part
5554 F16
LT5554
OUT
J3
50
TC4-1W
133.3
17.2
100
205
–1
23
4
option,
5554f