ADA4896-2 AD [Analog Devices], ADA4896-2 Datasheet - Page 18

• Manufacturer Part Number: ADA4896-2
• Description: 1 nV/?Hz, Low Power, Rail-to-Rail Output Amplifiers
• Manufacturer: AD [Analog Devices]

ADA4896-2/ADA4897-1
THEORY OF OPERATION
AMPLIFIER DESCRIPTION
The
amplifiers that consume 3 mA from supplies ranging from
3 V to 10 V. Utilizing the Analog Devices XFCB3 process, the
bandwidth is in excess of 200 MHz and unity gain stable and
the input structure results in an extremely low input of 1/f noise
for a high speed amplifier. The rail-to-rail output stage is
designed to drive a heavy feedback load required to achieve an
overall low output referred noise. Unlike other low noise unity
gain stable amplifiers, the large signal bandwidth has been
enhanced beyond the typical fundamental limits to meet more
demanding system requirements. The maximum offset of 500 μV
and drift of 1 μV/°C make the
excellent amplifier choice even when the noise is not needed
because there is minimal power penalty in achieving the low
input noise or the high bandwidth.
INPUT PROTECTION
The
events, withstanding human body model ESD events of 2.5 kV
and charge device model events of 1 kV with no measured
performance degradation. The precision input is protected
with an ESD network between the power supplies and diode
clamps across the input device pair, as shown in Figure 43.
For differential voltages above approximately 0.7 V, the diode
clamps start to conduct. Too much current can cause damage
due to excessive heating. If large differential voltages must
be sustained across the input terminals, it is recommended
that the current through the input clamps be limited to below
10 mA. Series input resistors that are sized appropriately for the
expected differential overvoltage provide the needed protection.
ADA4896-2/ADA4897-1
ADA4896-2/ADA4897-1
Figure 43. Input Stage and Protection Diodes
VCC
VEE
VP
ESD
ESD
TO THE REST OF THE AMPLIFIER
BIAS
are 1 nV/√Hz input noise
are fully protected from ESD
ADA4896-2/ADA4897-1
ESD
ESD
VN
an
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The ESD clamps start to conduct for input voltages that are
more than 0.7 V above the positive supply and input voltages
more than 0.7 V below the negative supply. It is recommended
that the fault current be limited to less than 10 mA if an
overvoltage condition is expected.
DISABLE OPERATION
Figure 44 shows the
DISABLE pin is left unconnected, the base of the input PNP
transistor is pulled high through the internal pull-up resistor to
the positive supply and the part is turned on. Pulling the
DISABLE pin to ≥2 V below the positive supply turns the part
off, reducing the supply current to approximately 18 μA for a
5 V voltage supply.
The DISABLE pin is protected with ESD clamps, as shown in
Figure 44. Voltages beyond the power supplies cause these
diodes to conduct. For protection of the DISABLE pin, the
voltage to this pin should not exceed 0.7 V of the supply voltage,
or the input current should be restricted to less than 10 mA
with a series resistor.
When the amplifier is disabled, its output goes to a high
impedance state. The output impedance decreases as frequency
increases; this effect can be observed in Figure 35. In disable
mode, a forward isolation of 50 dB can be achieved at 10 MHz.
Figure 42 shows the forward isolation vs. frequency data.
VCC
VEE
ADA4897-1
Figure 44. DISABLE Circuit
I
BIAS
AMPLIFIER
power-down circuitry. If the
BIAS
TO
ESD
ESD
DISABLE