ADL5363-EVALZ AD [Analog Devices], ADL5363-EVALZ Datasheet

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ADL5363-EVALZ

Manufacturer Part Number
ADL5363-EVALZ
Description
2300 MHz to 2900 MHz Balanced Mixer
Manufacturer
AD [Analog Devices]
Datasheet
FEATURES
RF frequency range of 2300 MHz to 2900 MHz
IF frequency range of dc to 450 MHz
Power conversion loss: 7.7 dB
SSB noise figure of 7.6 dB
Input IP3 of 31 dBm
Typical LO drive of 0 dBm
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed pad, 5 mm × 5 mm 20-lead LFCSP
1500 V HBM/1250 V FICDM ESD performance
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
GENERAL DESCRIPTION
The
mixer core along with integrated RF and local oscillator (LO)
balancing circuitry to allow for single-ended operation. The
ADL5363
performance over a 2300 MHz to 2900 MHz input frequency
range. The balanced passive mixer arrangement provides good
LO-to-RF leakage, typically better than −30 dBm, and excellent
intermodulation performance. The balanced mixer core also
provides extremely high input linearity, allowing the device to
be used in demanding cellular applications where in-band
blocking signals might otherwise result in the degradation of
dynamic performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
ADL5363
incorporates an RF balun to provide optimal
uses a highly linear, doubly balanced passive
2300 MHz to 2900 MHz Balanced Mixer,
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
The
in TDD applications where it is desirable to rapidly switch between
two local oscillators. LO current can be externally set using a
resistor to minimize dc current commensurate with the desired
level of performance. For low voltage applications, the ADL5363 is
capable of operation at voltages down to 3.3 V with substantially
reduced current. For low voltage operation, an additional logic
pin is provided to power down (<200 μA) the circuit when desired.
The
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
RF Frequency (MHz)
500 to 1700
1200 to 2500
2300 to 2900
NC = NO CONNECT
COMM
COMM
VPMX
RFCT
RFIN
ADL5363
ADL5363
1
2
3
4
5
VLO3
VCMI
20
FUNCTIONAL BLOCK DIAGRAM
6
LO Buffer and RF Balun
provides two switched LO paths that can be used
is fabricated using a BiCMOS high performance
LGM3
IFOP
19
GENERATOR
7
©2011 Analog Devices, Inc. All rights reserved.
Single
Mixer
ADL5367
ADL5365
ADL5363
BIAS
Figure 1.
VLO2
IFON
18
8
Single Mixer
and IF Amp
ADL5357
ADL5355
ADL5353
PWDN
LOSW
ADL5363
17
9
ADL5363
www.analog.com
COMM
NC
16
10
Dual Mixer
and IF Amp
ADL5358
ADL5356
ADL5354
15
14
13
12
11
LOI2
VPSW
VGS1
VGS0
LOI1

Related parts for ADL5363-EVALZ

ADL5363-EVALZ Summary of contents

Page 1

... TDD applications where it is desirable to rapidly switch between two local oscillators. LO current can be externally set using a resistor to minimize dc current commensurate with the desired level of performance. For low voltage applications, the ADL5363 is capable of operation at voltages down to 3.3 V with substantially reduced current. For low voltage operation, an additional logic pin is provided to power down (< ...

Page 2

... ADL5363 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... Performance........................................................................... 4 3.3 V Performance........................................................................ 4 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. Performance........................................................................... 7 3.3 V Performance...................................................................... 14 REVISION HISTORY 7/11—Revision 0: Initial Version   Upconversion.............................................................................. 15   ...

Page 3

... Tunable to >20 dB over a limited bandwidth Differential impedance 200 MHz Externally generated Device enabled, IF output to 90% of its final level Device disabled, supply current <5 mA Device enabled Device disabled ≤ 3.6 V only. Rev Page ADL5363 = 50 Ω, unless otherwise noted. O Min Typ Max 16 50 2300 2900 33||-0 ...

Page 4

... ADL5363 5 V PERFORMANCE 100 mA 25° 2535 MHz otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE Power Conversion Loss SSB Noise Figure Input Third-Order Intercept (IIP3) Input Second-Order Intercept (IIP2) Input 1 dB Compression Point (IP1dB) LO-to-IF Leakage LO-to-RF Leakage RF-to-IF Isolation IF/2 Spurious ...

Page 5

... Exposure to absolute 13 dBm maximum rating conditions for extended periods may affect 6.0 V device reliability. 5.5 V 0.5 W 25°C/W ESD CAUTION 150°C −40°C to +85°C −65°C to +150°C 260°C Rev Page ADL5363 ...

Page 6

... IFON, IFOP Differential IF Outputs. 20 VCMI No Connect. This pin can be grounded. EPAD (EP) Exposed pad. Must be soldered to ground. PIN 1 INDICATOR VPMX 1 15 LOI2 14 VPSW RFIN 2 ADL5363 RFCT 3 13 VGS1 TOP VIEW COMM 4 12 VGS0 (Not to Scale) COMM 5 11 LOI1 NOTES CONNECT. DO NOT CONNECT TO THIS PIN ...

Page 7

... +85° +25° 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 RF FREQUENCY (GHz) Figure 6. Input IP2 vs. RF Frequency 10.0 9.5 9.0 8 +25° +85° –40°C A 7.0 6.5 6.0 5.5 5.0 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 RF FREQUENCY (GHz) Figure 7. SSB Noise Figure vs. RF Frequency ADL5363 = –40°C 2.80 2.85 2.90 2.80 2.85 2.90 ...

Page 8

... ADL5363 100 mA 25° 2535 MHz otherwise noted. 140 130 120 5.25V 110 5.00V 100 4.75V –40 –30 –20 – TEMPERATURE (°C) Figure 8. Supply Current vs. Temperature 9.1 8.8 8.5 8.2 7.9 7.6 7.3 7.0 6.7 6.4 –40 –30 –20 – TEMPERATURE (°C) Figure 9 ...

Page 9

... +25° –40° 130 180 230 280 330 IF FREQUENCY (MHz) Figure 16. Input IP2 vs. IF Frequency 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6 130 180 230 280 330 IF FREQUENCY (MHz) Figure 17. SSB Noise Figure vs. IF Frequency ADL5363 380 430 380 430 ...

Page 10

... ADL5363 100 mA 25° 2535 MHz otherwise noted +85° +25° –6 –4 – POWER (dBm) Figure 18. Power Conversion Loss vs. LO Power –40° +25° +85°C ...

Page 11

... Figure 27. RF Port Return Loss, Fixed IF 0 –3 –6 –9 –12 SELECTED –15 –18 –21 –24 –27 UNSELECTED –30 –33 –36 –39 –42 –45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 LO FREQUENCY (GHz) Figure 28. LO Return Loss, Selected and Unselected ADL5363 –1 –2 –3 –4 0 380 430 2.80 2.85 2.90 3.10 ...

Page 12

... ADL5363 100 mA 25° 2535 MHz otherwise noted +85° +25° 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 RF FREQUENCY (GHz) Figure 29. LO Switch Isolation vs. RF Frequency –30 – –40°C –40 A –45 –50 –55 –60 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 RF FREQUENCY (GHz) Figure 30. RF-to-IF Isolation vs. RF Frequency – ...

Page 13

... Input IP3 vs. IF Bias Resistor Value 140 130 120 110 100 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 BIAS RESISTOR VALUE (Ω) Figure 38. Supply Current vs. Bias Resistor Value ADL5363 1800 ...

Page 14

... ADL5363 3.3 V PERFORMANCE 25° 2535 MHz otherwise noted +85° +25° –40° 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 RF FREQUENCY (GHz) Figure 39. Supply Current vs. RF Frequency at 3.3 V 9.0 8 +85°C 8 +25° –40°C A 7.0 6.5 6.0 5.5 5.0 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 RF FREQUENCY (GHz) Figure 40 ...

Page 15

... Figure 46. Power Conversion Loss vs. RF Frequency at 3.3 V, Upconversion S 2.70 2.75 2.80 2.85 2. Upconversion S Rev Page Ω, unless O 9.0 8.5 8.0 7 +85° +25° –40°C A 6.0 5.5 5.0 4.5 4.0 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 RF FREQUENCY (GHz –40° +25° +85° 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 RF FREQUENCY (GHz) Figure 47. Input IP3 vs. RF Frequency at 3.3 V, Upconversion ADL5363 2.80 2.85 2.90 2.80 2.85 2.90 ...

Page 16

... ADL5363 SPURIOUS PERFORMANCE (N × − (M × spur measurements were made using the standard evaluation board. Mixer spurious products are measured in dBc RF LO from the IF output power level. Data was measured only for frequencies less than 6 GHz. Typical noise floor of the measurement system = − ...

Page 17

... It is permissible to reduce the dc supply voltage VGS0 low as 3.3 V, further reducing the dissipated power of the part. (Note that no performance enhancement is obtained by reducing the value of these resistors and excessive dc power LOI1 11 dissipation may result LOSW NC Rev Page ADL5363 ...

Page 18

... V, resulting in substantial dc power savings. In addition, when operating with supply voltages below 3.6 V, the ADL5363 has a power-down mode that permits the dc current to drop to <200 μA. All of the logic inputs are designed to work with any logic family that provides a Logic 0 input level of less than 0 ...

Page 19

... BIAS LO +5V 10pF 10pF Figure 49. Typical Application Circuit Rev Page used to adjust the bias current BIAS LO features two logic control pins, VGS0 (Pin 12) and 10kΩ ADL5363 22pF LO2_IN 15 +5V 14 10pF 13 12 22pF LO1_IN 10kΩ ADL5363 ...

Page 20

... C5 0.01µF IF1_OUT R1 0Ω T1 C25 C24 560pF 560pF R14 0Ω VPMX LOI2 C21 10pF RFIN VPSW ADL5363 RFCT VGS1 C4 10pF COMM VGS0 COMM LOI1 VPOS R9 C6 1.1kΩ 10pF VPOS C8 10pF Figure 50. Evaluation Board Schematic Rev Page PWR_UP R21 10kΩ ...

Page 21

... VGS0 and VGS1 pins recommended to pull these two pins to ground for nominal operation. R9 sets the bias point for the internal LO buffers. Rev Page ADL5363 Default Conditions μF (size 0603), C6, C8, C20, C21 = 10 pF (size 0402 1.5 pF (size 0402 (size 0402 0.01 μ ...

Page 22

... ADL5363 Figure 51. Evaluation Board Top Layer Figure 52. Evaluation Board Ground Plane, Internal Layer 1 Figure 53. Evaluation Board Power Plane, Internal Layer 2 Figure 54. Evaluation Board Bottom Layer Rev Page ...

Page 23

... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 0.90 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADL5363ACPZ-R7 −40°C to +85°C ADL5363-EVALZ RoHS Compliant Part. 0.60 MAX 5.00 BSC SQ 0.60 MAX 15 16 4.75 0.65 BSC SQ BSC (BOTTOM VIEW 0.75 TOP VIEW 0.60 2.60 BSC 0.50 0.70 0.65 FOR PROPER CONNECTION OF 0.60 THE EXPOSED PAD, REFER TO ...

Page 24

... ADL5363 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09914-0-7/11(0) Rev Page ...

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