ADL5336-EVALZ AD [Analog Devices], ADL5336-EVALZ Datasheet - Page 18

• Manufacturer Part Number: ADL5336-EVALZ
• Description: Cascadable IF VGAs
• Manufacturer: AD [Analog Devices]

ADL5336
GAIN CONTROL INTERFACE
The
operate in either a gain-up mode or gain-down mode. In the
gain-up mode, with the MODE pin pulled high, the gain increases
with increasing gain voltages. In the gain-down mode, with the
MODE pin pulled low, the gain decreases with increasing gain
voltages. In both modes of operation, the gain control slope is
maintained at +37.5 dB/V or −38 dB/V (depending on mode
selection) over temperature, supply, and process as V
from 100 mV to 900 mV. To form an AGC loop with the on-board
detector around the VGA, the MODE pin has to be pulled low.
Each VGA has 24 dB of gain range that can be shifted as the
maximum gain is programmed.
The gain functions for MODE pulled high and low are given
respectively by
where V
INPUT AND OUTPUT IMPEDANCES
The
impedance. The output of each VGA is a low impedance buffer
with negative feedback within the programmable gain amplifier.
The negative feedback reduces the output impedance at low
frequencies, but the output impedance increases with increasing
frequency above 300 MHz.
Figure 61. Gain and Conformance Error vs. V
–10
–15
25
20
15
10
–5
ADL5336
ADL5336
Gain
Gain
5
0
0
GAIN
HIGH
LOW
0.1
is expressed in volts.
(dB) = −38 × V
(dB) = 37.5 × V
MODE = 0 V and MODE = 5 V for Both VGAs
has a linear-in-dB gain control interface that can
0.2
offers differential broadband, 200 Ω input
0.3
V
0.4
GAIN1
VGA1 GAIN
VGA1 GAIN
VGA2 GAIN
VGA2 GAIN
VGA1 ERROR
VGA1 ERROR
VGA2 ERROR
VGA2 ERROR
GAIN
/V
0.5
GAIN
GAIN2
+ 24.8
− 14
0.6
(V)
GAIN1
0.7
/V
GAIN2
0.8
for Gain Code 11, and
0.9
GAIN
1.0
4
3
2
1
0
–1
–2
–3
–4
varies
Rev. B | Page 18 of 32
AGC OPERATION
The internally connected square law detectors are connected to
the outputs of the VGAs through a programmable attenuator.
The detector compares the output of the attenuator to an
internal reference of 63 mV rms. The AGC loop is closed by
connecting the DTO1/DTO2 pins to the GAIN1/GAIN2 pins,
and having the MODE pin pulled low, configuring the VGAs
for a negative gain slope.
If the attenuator is programmed to pass the full VGA output,
the AGC forces the output of the VGA to 63 mV rms, as long
as the gain required is within the gain range of the VGA. If the
attenuator is programmed to attenuate the VGA output by 21 dB
(Setpoint Word 111) and the AGC loop is closed, the AGC
function forces the VGA output to 707 mV rms. If the gain
required to achieve the programmed target output level is out of
the VGA range, the GAINx pin rails to either VPOS/2 or GND.
If the amplifier is operated in VGA mode or the detector is not
otherwise being used, the setpoint should be programmed to
maximum attenuation so that the VGA output does not overdrive
the input to the detector, adversely affecting both the detector
and VGA output.
Figure 62. RMS Detection Diagram (Shows the Signal Path from VGA1/VGA2
GAIN1/
GAIN2
Output to Squarer Cell)
X
2
+
SETPOINT
CONTROL
SPI
–
C
DTO1/
DTO2
AGC
X
2
Data Sheet
63mV rms
REF