ADL5201-EVALZ AD [Analog Devices], ADL5201-EVALZ Datasheet - Page 19

• Manufacturer Part Number: ADL5201-EVALZ
• Description: Wide Dynamic Range, High Speed
• Manufacturer: AD [Analog Devices]

Data Sheet
Figure 54 shows the
pass filter into the AD9467. The
to 250 MSPS ADC with a buffered wideband input that presents
a 530 Ω differential input impedance and requires a 2 V or 2.5 V
input swing to reach full scale. For optimum performance, the
ADL5201
transformer or input balun.
Figure 54 uses a 1:3 impedance transformer to provide the
150 Ω input impedance of the
The outputs of the
inductors, and the two 0.1 μF capacitors on the outputs decouple
the 5 V inductor voltage from the input common-mode voltage
of the AD9467. The two 75 Ω resistors provide the 150 Ω load to
the ADL5201, whose gain is load dependent. The 47 nH induc-
tors and 14 pF capacitor constitute the (100 MHz − 1 dB) low-pass
filter. The two 33 Ω isolation resistors suppress any switching
currents from the ADC input sample-and-hold circuitry. The
circuit depicted in Figure 54 provides variable gain, isolation,
filtering, and source matching for the AD9467. By using this
circuit with the
an SNR of 68 dB and an SFDR performance of 88 dBc are
achieved at 100 MHz, as shown in Figure 56.
–10
–12
–11
–1
–2
–3
–4
–5
–6
–7
–8
–9
Figure 55. Measured Frequency Response of the Wideband
0
0
should be driven differentially, using an impedance
20
ADL5201
ADC Interface Shown in Figure 54
40
ADL5201
ADL5201
60
AC
50Ω
in a gain of 20 dB (maximum gain),
FREQUENCY (MHz)
80
are biased through the two 1 μH
ADL5201
driving a two-pole, 100 MHz, low-
100
Figure 54. Wideband ADC Interfacing Example Featuring the
AD9467
1:3
120
with a matched input.
is a 16-bit, 200 MSPS
140
0.1µF
0.1µF
160
ADL5201
INTERFACE
DIGITAL
180
5V
200
5V
5V
Rev. 0 | Page 19 of 28
1µH
1µH
0.1µF
0.1µF
75Ω
75Ω
The two-tone 100 MHz IMDs of two 1 V p-p signals have
an SFDR of greater than 91 dBc, as shown in Figure 57.
V
REF
Figure 56. Measured Single-Tone Performance of the Circuit Shown
–105
–120
–135
–150
–105
–120
–135
–150
–15
–30
–45
–60
–75
–90
–15
–30
–45
–60
–75
–90
47nH
47nH
0
0
ADL5201
0
Circuit Shown in Figure 54 for a 100 MHz Input Signal
0
Figure 57. Measured Two-Tone Performance of the
SNR = 68dB
SFDR = 88dBc
NOISE FLOOR = –114dBFS
FUND = –1.05dBFS
SECOND = –94.7dBc
THIRD = –88.75dBc
5
FUND1 = –6.682dBFS
FUND2 = –7.096dBFS
2f1 – f2 = –93.2dBFS
2f2 – f1 = –92.58dBc
NOISE FLOOR = –115.3dBFS
f2 – f1
15
14pF
15
in Figure 54 for a 100 MHz Input Signal
33Ω
33Ω
and the
30
30
2f2 + f1
AD9467
AD9467
45
45
V
3
REF
FREQUENCY (MHz)
2f1 + f2
FREQUENCY (MHz)
2
f1 + f2
+
60
60
75
75
2f2 – f1
90
90
+
6
105
105
4
2f1 – f2
ADL5201
120
120