AD589UH AD [Analog Devices], AD589UH Datasheet
AD589UH
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AD589UH Summary of contents
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FEATURES Fast Conversion Time On-Chip Track/Hold Low Total Unadjusted Error: 1 LSB Full Power Signal Bandwidth: 50 kHz Single +5 V Supply 100 ns Data Access Time Low Power (15 mW typ) Low Cost Standard 18-Lead DlPs ...
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AD7575–SPECIFICATIONS Parameter J, A Versions ACCURACY Resolution 8 Total Unadjusted Error 2 Relative Accuracy 1 Minimum Resolution for Which No Missing Codes Is Guaranteed 8 Full-Scale Error + MIN MAX 2 Offset Error +25 ...
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TIMING SPECIFICATIONS Limit at +25 C Limit at T Parameter (All Versions) ( Versions 100 100 100 100 3 t 100 100 ...
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AD7575 DIP/SOIC REF TP AIN 3 16 BUSY AGND 4 15 AD7575 CLK 5 14 DB0 (LSB) TOP VIEW (Not to Scale) DB7 (MSB DB1 DB6 7 12 DB2 ...
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CS RD BUSY HIGH IMPEDANCE DATA BUS Figure 3. Slow Memory Interface Timing Diagram TIMING AND CONTROL OF THE AD7575 The two logic inputs on the AD7575, CS and RD, control both the starting of conversion and the reading of ...
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AD7575 BUSY t 3 HIGH DATA IMPEDANCE BUS Figures 6 and 7 show connection diagrams for interfacing the AD7575 in the ROM Interface mode. Figure 6 shows the AD7575 interface to the 6502/6809 microprocessors while the ...
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A SAMPLED-DATA INPUT The AD7575 makes use of a sampled-data comparator. The equivalent input circuit is shown in Figure 9. When a conversion starts, switch S1 is closed, and the equivalent input capacitance is charged With a ...
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AD7575 INTERNAL/EXTERNAL CLOCK The AD7575 can be used with its own internal clock or with an externally applied clock. In either case, the clock signal appear- ing at the CLK pin is divided internally by two to provide an internal ...
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UNIPOLAR OPERATION The basic operation for the AD7575 is in the unipolar single supply mode. Figure 15 shows the circuit connections to achieve this, while the nominal transfer characteristic for unipolar opera- tion is given in Figure 16. Since the ...
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AD7575 APPLICATION HINTS 1. NOISE: Both the input signal lead to AIN and the signal return lead from AGND should be kept as short as possible to minimize input-noise coupling. In applications where this is not possible, either a shielded ...
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... C to +70 C AD589MH +70 C AD589SH – +125 C AD589TH – +125 C AD589UH – +125 C *Excluding resistor and offset drift. REV. B Taking the 25 C measurement as the starting point, the full-scale error introduced is always in the negative direction whether the temperature goes to T seen from the AD589 temperature characteristic shown in Fig- ure 20 ...
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AD7575 18-Lead Plastic DIP (N-18) 0.91 (23.12) 0.89 (22.61 0.26 (6.61) 0.24 (6.10 PIN 1 0.175 (4.45) 0.18 (4.58) 0.12 (3.05) MAX 0.02 (0.508) 0.105 (2.67) 0.065 (1.66) 0.015 (0.381) 0.095 (2.42) 0.045 (1.15) SEATING PLANE ...