LT3493-3 LINER [Linear Technology], LT3493-3 Datasheet - Page 16

• Manufacturer Part Number: LT3493-3
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LT3493-3
response. Large electrolytic capacitors may have an ESR
large enough to create an additional zero, and the phase
lead may not be necessary.
If the output capacitor is different than the recommended
capacitor, stability should be checked across all operating
conditions, including load current, input voltage and tem-
perature. The LT1375 data sheet contains a more thor-
ough discussion of loop compensation and describes how
to test the stability using a transient load.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 11 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents flow in the LT3493-3’s V
diode (D1) and the input capacitor (C2). The loop formed
by these components should be as small as possible and
tied to system ground in only one place. These compo-
nents, along with the inductor and output capacitor,
should be placed on the same side of the circuit board, and
their connections should be made on that layer. Place a
16
U
SHUTDOWN
U
Figure 10. A Good PCB Layout Ensures Proper, Low EMI Operation
V
IN
IN
and SW pins, the catch
W
: VIAS TO LOCAL GROUND PLANE
: OUTLINE OF LOCAL GROUND PLANE
U
C2
D1
local, unbroken ground plane below these components,
and tie this ground plane to system ground at one location,
ideally at the ground terminal of the output capacitor C1.
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB node small so that the ground pin and
ground traces will shield it from the SW and BOOST nodes.
Include vias near the exposed GND pad of the LT3493-3 to
help remove heat from the LT3493-3 to the ground plane.
High Temperature Considerations
The die temperature of the LT3493-3 must be lower than
the maximum rating of 125°C. This is generally not a
concern unless the ambient temperature is above 85°C.
For higher temperatures, care should be taken in the
layout of the circuit to ensure good heat sinking of the
LT3493-3. The maximum load current should be derated
as the ambient temperature approaches 125°C. The die
temperature is calculated by multiplying the LT3493-3
power dissipation by the thermal resistance from junction
to ambient. Power dissipation within the LT3493-3 can be
estimated by calculating the total power loss from an
efficiency measurement and subtracting the catch diode
C1
3493-3 F11
SYSTEM
GROUND
V
OUT
3493-3f