ADG1633 AD [Analog Devices], ADG1633 Datasheet

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ADG1633

Manufacturer Part Number
ADG1633
Description
Manufacturer
AD [Analog Devices]
Datasheet

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FEATURES
4.5 Ω typical on resistance
1 Ω on-resistance flatness
Up to 206 mA continuous current
±3.3 V to ±8 V dual-supply operation
3.3 V to 16 V single-supply operation
No V
3 V logic-compatible inputs
Rail-to-rail operation
ADG1633
ADG1634
APPLICATIONS
Communication systems
Medical systems
Audio signal routing
Video signal routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Relay replacements
GENERAL DESCRIPTION
The ADG1633 and ADG1634 are monolithic industrial CMOS
(iCMOS®) analog switches comprising three independently
selectable single-pole, double-throw (SPDT) switches and
four independently selectable SPDT switches, respectively.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An
EN input on the ADG1633 (LFCSP and TSSOP packages) and
ADG1634 (LFCSP package only) is used to enable or disable
the devices. When disabled, all channels are switched off.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications, where low distortion is critical. iCMOS
construction ensures ultralow power dissipation, making the parts
ideally suited for portable and battery-powered instruments.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
16-lead TSSOP and 16-lead, 3 mm × 3 mm LFCSP
20-lead TSSOP and 20-lead, 4 mm × 4 mm LFCSP
L
supply required
+12 V, +5 V, and +3.3 V Switches
4.5 Ω R
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
ON
FUNCTIONAL BLOCK DIAGRAMS
, Triple/Quad SPDT ±5 V,
Figure 1. ADG1633 TSSOP and LFCSP_VQ
S1A
S1B
S2B
S2A
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
S1A
S1B
S2B
S2A
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
S1A
S1B
S2B
S2A
SWITCHES SHOWN FOR
A 1 INPUT LOGIC.
IN1
IN2
D1
D2
D1
D2
D1
D2
Figure 3. ADG1634 LFCSP_VQ
Figure 2. ADG1634 TSSOP
IN1 IN2 IN3 IN4
ADG1633/ADG1634
©2009 Analog Devices, Inc. All rights reserved.
IN1 IN2 IN3 EN
ADG1633
ADG1634
ADG1634
LOGIC
LOGIC
EN
S3B
D3
S3A
S4A
D4
S4B
IN4
IN3
S3B
D3
S3A
S4A
D4
S4B
S3B
D3
S3A
www.analog.com

Related parts for ADG1633

ADG1633 Summary of contents

Page 1

... SPDT switches, respectively. All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels input on the ADG1633 (LFCSP and TSSOP packages) and ADG1634 (LFCSP package only) is used to enable or disable the devices. When disabled, all channels are switched off. ...

Page 2

... ADG1633/ADG1634 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagrams ............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 ±5 V Dual Supply ......................................................................... Single Supply ........................................................................ Single Supply .......................................................................... 5 3.3 V Single Supply ....................................................................... 6 REVISION HISTORY 7/09—Revision 0: Initial Version Continuous Current per Channel ..................................7 Absolute Maximum Ratings ............................................................8 ESD Caution...................................................................................8 Pin Configurations and Function Descriptions ...

Page 3

... Rev Page ADG1633/ADG1634 Unit Test Conditions/Comments V Ω typ V = ±4 −10 mA; see Figure Ω max V = ±4 ±4 Ω typ V = ±4 − Ω ...

Page 4

... ADG1633/ADG1634 12 V SINGLE SUPPLY ± 10 GND = 0 V, unless otherwise noted Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance ( On-Resistance Match Between Channels (∆R On-Resistance Flatness (R ) FLAT(ON) LEAKAGE CURRENTS Source Off Leakage, I (Off) S Drain Off Leakage, I (Off) ...

Page 5

... MHz typ 21 pF typ 37 pF typ 62 pF typ 0.001 μA typ 1.0 μA max 3.3/16 V min/max Rev Page ADG1633/ADG1634 Test Conditions/Comments 4 −10 mA; see Figure 4 4 − 4 − ...

Page 6

... ADG1633/ADG1634 3.3 V SINGLE SUPPLY GND = 0 V, unless otherwise noted Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance ( On-Resistance Match Between Channels (∆R On-Resistance Flatness (R ) FLAT(ON) LEAKAGE CURRENTS Source Off Leakage, I (Off ) S Drain Off Leakage, I (Off ) D Channel On Leakage (On) ...

Page 7

... CONTINUOUS CURRENT PER CHANNEL Table 5. ADG1633 Parameter CONTINUOUS CURRENT − TSSOP (θ = 112.6°C/W) JA LFCSP (θ = 48.7°C/ TSSOP (θ = 112.6°C/W) JA LFCSP (θ = 48.7°C/ TSSOP (θ = 112.6°C/W) JA LFCSP (θ ...

Page 8

... ADG1633/ADG1634 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 7. Parameter Rating GND −0 + GND +0 − Analog Inputs V − 0 mA, whichever occurs first Digital Inputs 1 GND − 0 mA, whichever occurs first ...

Page 9

... TOP VIEW S2B 5 12 (Not to Scale S2A 7 10 IN2 8 9 Figure 4. ADG1633 TSSOP Pin Configuration Table 8. ADG1633 Pin Function Descriptions Pin No. TSSOP LFCSP_VQ Mnemonic Description Most Positive Power Supply Potential S1A Source Terminal 1A. Can be an input or an output. ...

Page 10

... ADG1633/ADG1634 IN1 1 20 S1A S1B 4 17 ADG1634 TOP VIEW GND 6 15 (Not to Scale) S2B S2A 9 12 IN2 CONNECT Figure 6. ADG1634 TSSOP Pin Configuration Table 10. ADG1634 Pin Function Descriptions Pin No. TSSOP LFCSP_VQ Mnemonic Description ...

Page 11

... Figure 12. On Resistance vs + – Figure 13. On Resistance vs. V Rev Page ADG1633/ADG1634 V = 12V +125° +85° +25° –40° SOURCE OR DRAIN VOLTAGE (V) ...

Page 12

... (OFF) – (OFF) + – (OFF) + – (OFF) – – TEMPERATURE (°C) Figure 17. ADG1633 Leakage Currents vs. Temperature, 3.3 V Single Supply I PER CHANNEL 25° +12V + – + ...

Page 13

... LOAD = 110Ω T 0.6 0.5 0.4 0.3 0.2 0.1 0 100M –20 –40 –60 –80 –100 –120 1k 100M 1G Rev Page ADG1633/ADG1634 100k 1M 10M 100M FREQUENCY (Hz) Figure 23. On Response vs. Frequency = 25° +3.3V p +5V 3.5V p +5V –5V p-p ...

Page 14

... OUT OUT L 100Ω 35pF GND Figure 30. Break-Before-Make Delay 0.1µ ENABLE ADG1633 DRIVE (V V INx S1A S INx S1B V OUT INx OUT OUTPUT GND L 100Ω 35pF ( Figure 31. Enable Delay Rev ...

Page 15

... ANALYZER OUT 50Ω OUT R L 50Ω CHANNEL-TO-CHANNEL CROSSTALK = 20 log 0.1µF NETWORK ANALYZER 50Ω OUT R L 50Ω Rev Page ADG1633/ADG1634 ON OFF × ΔV INJ L OUT 0.1µF 0.1µ 50Ω ...

Page 16

... ADG1633/ADG1634 TERMINOLOGY R ON Ohmic resistance between Terminal D and Terminal S. ΔR ON The difference between the R of any two channels FLAT(ON) The difference between the maximum and minimum value of on resistance measured. I (Off) S Source leakage current when the switch is off. I (Off) D Drain leakage current when the switch is off. ...

Page 17

... TOP VIEW BOTTOM VIEW 0.40 0.30 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WEED. Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ × 3 mm, Very VeryThin Quad (CP-16-22) Dimensions shown in millimeters Rev Page ADG1633/ADG1634 0.75 0.60 0. 1.75 PAD 1. 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO ...

Page 18

... ADG1633/ADG1634 COPLANARITY PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE 6.60 6.50 6. 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.20 0.05 0.09 0.30 0.19 SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 39. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 0.50 3.75 BSC BSC SQ 11 0.50 TOP VIEW 0.40 0.30 0.80 MAX 0.65 TYP ...

Page 19

... Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Rev Page ADG1633/ADG1634 Package EN Pin Option Branding Yes ...

Page 20

... ADG1633/ADG1634 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08319-0-7/09(0) Rev Page ...

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