HD6417040AF28 RENESAS [Renesas Technology Corp], HD6417040AF28 Datasheet - Page 151
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HD6417040AF28
Manufacturer Part Number
HD6417040AF28
Description
Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417040AF28.pdf
(923 pages)
- Current page: 151 of 923
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IRQOUT = high level *
Branches to exception
IRQOUT = low level *
Copy accept-interrupt
I3 to I0: Interrupt mask bits of status register
Notes: *1
Save SR to stack
Save PC to stack
Reads exception
level to I3 to I0
service routine
execution state
vector table
Interrupt?
Program
NMI?
*2
Yes
Yes
IRQOUT is the same signal as the interrupt request signal to the CPU (see
figure 6.1). Thus, it is output when there is a higher priority interrupt request
than the one in the I3 to I0 bits of the SR.
When the accepted interrupt is sensed by edge, the IRQOUT pin becomes
high level at the point when the CPU starts interrupt exception processing
instead of instruction execution (before SR is saved to the stack).
If the interrupt controller has accepted another interrupt with a higher priority
and has output an interrupt request to the CPU, the IRQOUT pin will remain
low level.
User break?
1
No
No
2
Yes
Yes
interrupt?
level 14?
I3 to I0
Level 15
No
No
Yes
Yes
No
interrupt?
level 13?
I3 to I0
Level 14
No
Yes
Yes
No
interrupt?
I3 to I0 =
Level 1
level 0?
Yes
No
No
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