ISD-T360 ETC [List of Unclassifed Manufacturers], ISD-T360 Datasheet - Page 21

• Manufacturer Part Number: ISD-T360
• Description: VoiceDSP Digital Speech Processor with Master/Slave, Full-Duplex Speakerphone, Multiple Flash and ARAM/DRAM Support
• Manufacturer: ETC [List of Unclassifed Manufacturers]

1—HARDWARE
1.2.6
The ISD-T360 provides an on chip interface for
analog and digital telephony, supporting master
and slave codec interface modes. In master
mode, the ISD-T360 controls the operation of the
codec for use in analog telephony. In the slave
mode, the ISD-T360 codec interface is controlled
by an external source. This mode is used in digital
telephony (i.e., ISDN or DECT lines). The slave
mode is implemented with respect to IOM-2™/
CGI specifications.
See Table 1-7 for codec options for the ISD-
T360SB (ISD supports compatible codecs in addi-
tion to those listed below).
The codec interface supports the following fea-
tures:
• Master Mode or Slave Mode.
• 8- or 16-bit Channel Width.
• Long (Variable) or Short (Fixed) Frame
• Single or Double Bit (Slave Mode Only)
• Single or Dual Channel Codecs
• One or Two Codecs
• Multiple Clock And Sample Rates.
• One or Two Frame Sync Signals
This codec interface uses five signals: CDIN, CD-
OUT, CCLK, CFS0, and CFS1. The CDIN, CDOUT,
CCLK, and CFS0 pins are connected to the first
codec. The second codec is connected to
ISD
National
Semiconductor
National
Semiconductor
Oki
Oki
Macronix
Lucent
Lucent
Protocol.
Clock Rate.
Manufacturer
THE CODEC INTERFACE
Codec Device Name
MX93002FC
T7502
T7503
TP3054
TP 3057
MSM7533V
MSM 7704
Table 1-7: Supported Codec Devices
Single codec
Single codec
Dual codec
Dual codec
Dual codec
Dual codec
Dual codec
Characteristics
CDIN, CDOUT, CCLK, and CFS1 pins. Data is
transferred to the codec through the CDOUT
output pin. Data is read from the codec through
the CDIN input pin. The CCLK and CFS0 pins are
output in Master Mode and input in Slave Mode.
The CFS1 is an output pin.
Short Frame Protocol
When the short frame protocol is configured,
eight or sixteen data bits are exchanged with
each codec in each frame (i.e., the CFS0 cycle).
Data transfer begins when CFS0 is set to 1 for one
CCLK cycle. The data is then transmitted, bit by
bit, via the CDOUT pin. Concurrently, the re-
ceived data is shifted in through the CDIN pin.
Data is shifted one bit per CCLK cycle. After the
last bit has been shifted, CFS1 is set to 1 for one
CCLK cycle. Then, the data from the second co-
dec is shifted out via CDOUT, concurrently with
the inward shift of the data received via CDIN.
Long Frame Protocol
When long frame protocol is configured, eight or
sixteen data bits are exchanged with each co-
dec, as for the short frame protocol. However,
for the long frame protocol, data transfer starts
by setting CFS0 to 1 for eight or sixteen CCLK cy-
cles. Short or long frame protocol is available in
both Master and Slave modes. Figure 1-11 illus-
trates an example of short frame protocol with
an 8-bit channel width.
5 V
5 V
5 V
3.3 V
5 V
5 V
5 V
Operating Voltage
Conversion Type
µ-Law
A-Law
µ-Law, A-Law
µ-Law, A-Law, LV
µ-Law
A-Law
µ-Law
1-13