AD9389AKCPZ-80 AD [Analog Devices], AD9389AKCPZ-80 Datasheet - Page 5

• Manufacturer Part Number: AD9389AKCPZ-80
• Description: High Performance HDMI/DVI Transmitter
• Manufacturer: AD [Analog Devices]

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
2, 39 to 47,
50 to 63
6
3
4
5
18
20
7
8
9 to 12
13
14
26
21, 22
31, 32
27, 28
24, 25
32
19, 23, 29
Mnemonic
D[23:0]
CLK
DE
HSYNC
VSYNC
EXT_SW
HPD
S/PDIF
MCLK
I
SCLK
LRCLK
PD/A0
TxC−/TxC+
Tx2−/Tx2+
Tx1−/Tx1+
Tx0−/Tx0+
INT
AVDD
2
S[3:0]
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
P
1
NC = NO CONNECT
HSYNC
VSYNC
Description
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V.
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.
Horizontal SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Vertical SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground.
Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to
5.0 V CMOS logic level.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips
digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Reference Clock. 128 × N × f
256 × f
I
through I
I
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
Power-Down Control and I
PD/A0 pin state when the supplies are applied to the AD9389A. 1.8 V to 3.3 V CMOS logic level.
Differential Clock Output. Differential clock output at pixel clock rate; transition minimized
differential signaling (TMDS) logic level.
Differential Output Channel 2. Differential output of the red data at 10 × the pixel clock rate;
TMDS logic level.
Differential Output Channel 1. Differential output of the green data at 10 × the pixel clock rate;
TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10 × the pixel clock rate;
TMDS logic level.
Interrupt. CMOS logic level. A 2 kΩ pull up resistor to interrupt the microcontroller IO supply is
recommended.
1.8 V Power Supply for TMDS Outputs.
LRCLK
S/PDIF
2
2
DVDD
MCLK
SCLK
PVDD
PVDD
S Audio Data Inputs. These represent the eight channels of audio (two per input) available
S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
CLK
I
I
I
I
2
2
2
2
DE
D0
S0
S1
S2
S3
10
11
12
13
14
15
16
S
1
2
3
4
5
6
7
8
9
, 384 × f
2
S. Supports CMOS logic levels from 1.8 V to 3.3 V.
PIN 1
INDICATOR
S
, or 512 × f
Figure 2. Pin Configuration
Rev. 0 | Page 5 of 12
(Not to Scale)
AD9389A
TOP VIEW
2
S
C Address Selection. The I
. 1.8 V to 3.3 V CMOS logic level.
S
with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (f
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DVDD
D15
D16
D17
D18
D19
D20
D21
D22
D23
NC
NC
SDA
SCL
DDCSDA
DDCSCL
2
C address and the PD polarity are set by the
AD9389A
S
),