Z53C80SCSI ZILOG [Zilog, Inc.], Z53C80SCSI Datasheet

Z53C80SCSI

Manufacturer Part Number

Z53C80SCSI

Description

SMALL COMPUTER SYSTEM INTERFACE (SCSI)

Manufacturer

ZILOG [Zilog, Inc.]

Datasheet

1.Z53C80SCSI.pdf (40 pages)

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GENERAL DESCRIPTION

PS97SCC0200

FEATURES

The Z53C80 SCSI (Small Computer System Interface)

controller is designed to implement the SCSI protocol as

defined by the ANSI X3.131-1986 standard, and it is fully

compatible with the industry standard 5380. The device is

capable of operating both as a Target and as an Initiator.

Special high-current open-drain outputs enable it to directly

interface to the SCSI bus. The Z53C80 has the necessary

interface hook-ups which allow the system CPU to

communicate with it as with any other peripheral device.

The CPU can read from, or write to, the SCSI registers

which are addressed as standard or memory-mapped

I/Os.

The Z53C80 increases the system performance by

minimizing the CPU intervention in DMA operations which

the SCSI controls. The CPU is interrupted by the SCSI

when it detects a bus condition that requires attention. It

also supports arbitration and reselection. The Z53C80 has

the proper handshake signals to support normal and block

mode DMA operations with most DMA controllers available.

ILOG

Pin Compatible with the Industry Standard 5380

44-Pin PLCC or 48-Pin DIP Package Styles

DMA or Programmed I/O Data Transfers

Arbitration Support

Supports Normal or Block Mode DMA

Memory or I/O Mapped CPU Interface

The added enhancement known as the “Glitch Eater” is

used to minimize effects of bus reflection on improperly

terminated SCSI bus applications. The high frequency

reflections that can occur on the SCSI bus are filtered out,

reducing the sensitivity of the inputs, specifically /REQ and

/ACK to bus signal reflections. Figure 1 shows a worst case

input waveform (labeled A), along with the filtered input

(labeled B) and the output of a Schmitt trigger used to

provide the hysteresis required on SCSI inputs (labeled

C). This enhancement is a requirement for the device to

function properly in a Apple Macintosh

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.,

B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Z53C80

Apple Macintosh is a registered trademark of Apple Computer, Inc.

RODUCT

MALL

YSTEM

Connection

Asynchronous Interface (Supports 3 MB/s)

Direct SCSI Bus Interface with On-Board 48 mA Drivers

Supports Target and Initiator Roles

Meets SCSI Protocol as Defined in ANSI X3.131-1986

Standard

Added “Glitch Eater” Enhancement to Minimize Bus

Reflection

Ground

Power

OMPUTER

PECIFICATION

NTERFACE

Circuit

GND

(SCSI)

environment.

Device

Z53C80 SCSI

Related parts for Z53C80SCSI

Z53C80SCSI Summary of contents

Page 1

Z ILOG FEATURES Pin Compatible with the Industry Standard 5380 44-Pin PLCC or 48-Pin DIP Package Styles DMA or Programmed I/O Data Transfers Arbitration Support Supports Normal or Block Mode DMA Memory or I/O Mapped CPU Interface GENERAL DESCRIPTION The ...

Page 2

Z ILOG GENERAL DESCRIPTION (Continued) 5.50 5.00 4.50 4.00 3.50 3.00 2.50 2.00 A 1. -.50 0 20.0 Figure 1. Worst Case Unfiltered Input (A), Filtered Input (B), Output of Schmitt-Trigger Used to Provide ...

Page 3

Z ILOG /IOR /IOW /CS CPU BUS Interface /RESET A2-A0 D7-D0 /RESET READY PS97SCC0200 /DB7-/DB0, /DBP /ACK /ATN /BSY /MSG 48 mA SCSI Transceivers Interface Data Control Input Logic Register DMA Interrupt Logic Logic Figure 2a. SCSI Block Diagram D7-D0 ...

Page 4

Z ILOG GENERAL DESCRIPTION (Continued) /DB7 1 48 /RST 2 47 GND 3 46 /BSY 4 45 /SEL 5 44 /ATN /RESET 8 41 IRQ 9 40 DRQ 10 39 /EOP 11 38 Z53C80 /DACK ...

Page 5

Z ILOG PIN DESCRIPTION Microprocessor Bus A2-A0 Address Lines (Input). Address lines are used to access all internal registers with /CS, /IOR, and /IOW. /CS /Chip Select (Input, active Low) . /CS, in conjunction with /RD or /WR, enables the ...

Page 6

Z ILOG SCSI BUS The following signals are all Bi-directional, active Low, open-drain, with 48 mA sink capacity. All pins interface directly with the SCSI Bus. /ACK /Acknowledge (Bi-directional, Open-Drain, Active Low). /ACK is driven by the Initiator and indicates ...

Page 7

Z ILOG FUNCTIONAL DESCRIPTION General. The Small Computer System interface (SCSI) device has a set of eight registers that are controlled by the CPU. By reading and writing the appropriate registers, the CPU may initiate any SCSI Bus activity or ...

Page 8

Z ILOG FUNCTIONAL DESCRIPTION (Continued) Input Data Register. Address 6 (Read Only). The input Data Register (Figure read-only register that is used to read latched data from the SCSI Bus. Data is latched either during a DMA ...

Page 9

Z ILOG The following paragraphs describe the operation of all bits in the Initiator Command Register. Bit 0. Assert Data Bus. The Assert Data Bus bit, when set, allows the contents of the Output Data Register to be enabled as ...

Page 10

Z ILOG FUNCTIONAL DESCRIPTION (Continued) Bit 0. Arbitrate. The Arbitrate bit is set (1) to start the Arbitration process. Prior to setting this bit, the Output Data Register should contain the proper SCSI device ID value. Only one data bit ...

Page 11

Z ILOG Bit 7. Last Byte Sent (Read Only). The End Of DMA Transfer bit (Bus and Status Register, bit 7) only indicates when the last byte was received from the DMA controller. The Last Byte Sent bit can be ...

Page 12

Z ILOG FUNCTIONAL DESCRIPTION (Continued) Bus and Status Register. Address 5 (Read Only). The Bus and Status Register (Figure 14 read-only register which can be used to monitor the remaining SCSI control signals not found in the Current ...

Page 13

Z ILOG Start DMA Initiator Receive. Address 7 (Write Only). This register is written to initiate a DMA receive from the SCSI Bus to the DMA, for Initiator operation only. The DMA Mode bit (bit 6) must be False (0) ...

Page 14

Z ILOG FUNCTIONAL DESCRIPTION (Continued /DBP /SEL I//O C//D /MSG /REQ /BSY /RST Figure 16. Current SCSI Bus Status Register End of Process (EOP) Interrupt. An End Of Process signal ...

Page 15

Z ILOG /ACK /ATN Busy Error Phase Match Interrupt Request Active Parity Error DMA Request End of DMA Figure 19. Bus and Status Register ...

Page 16

Z ILOG FUNCTIONAL DESCRIPTION (Continued) A phase mismatch prevents the recognition of /REQ and removes the chip from the bus during an Initiator send operation (/DB7-/DB0 and /DBP will not be driven even through the Assert Data Bus bit (Initiator ...

Page 17

Z ILOG Reset Conditions. Three possible reset situations exist with the Z53C80, as follows: Hardware Chip Reset. When the signal RST is active for at least 100 ns, the Z53C80 device is re-initialized and all internal logic and control registers ...

Page 18

Z ILOG FUNCTIONAL DESCRIPTION (Continued) Pseudo DMA Mode. To avoid monitoring and asserting the request/acknowledgment handshake signals for programmed I/O transfers, the system may be designed to implement a pseudo DMA mode. This mode is implemented by programming the Z53C80 ...

Page 19

Z ILOG READ REGISTERS Address: 0 (Read Only /DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7 Figure 27. Current SCSI Data Register Address: 1 (Read Only ...

Page 20

Z ILOG READ REGISTERS (Continued) Address: 6 (Read Only /DB0 /DB1 /DB2 /DB3 /DB4 /DB5 /DB6 /DB7 Figure 33. Input Data Register WRITE REGISTERS Address: 0 Write Only ...

Page 21

Z ILOG Address: 2 (Write Only Arbitrate DMA Mode Monitor /BSY Enable /EOP Interrupt Enable Parity Interrupt Enable Parity Checking Target Mode "0" Figure 37. Mode Register Address: 3 (Write Only) D7 ...

Page 22

Z ILOG ABSOLUTE MAXIMUM RATINGS Voltages on all pins with respect to GND ................................. –0.3V to +7.0V Operating Ambient Temperature ................................... † Storage Temperature ............................ – +150 C Note: † See Ordering Information STANDARD TEST CONDITIONS The DC ...

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