ADUC7025BCPZ32-RL7 AD [Analog Devices], ADUC7025BCPZ32-RL7 Datasheet - Page 68

• Manufacturer Part Number: ADUC7025BCPZ32-RL7
• Description: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
• Manufacturer: AD [Analog Devices]

ADuC7019/20/21/22/24/25/26/27
I
The I
discussed in this section.
I2CxMSTA Registers
Name
I2C0MSTA
I2C1MSTA
I2CxMSTA are status registers for the master channel.
Table 60. I2C0MSTA MMR Bit Descriptions
Bit
7
6
5
4
3
2
1
0
I2CxSSTA Registers
Name
I2C0SSTA
I2C1SSTA
I2CxSSTA are status registers for the slave channel.
2
C Registers
2
C peripheral interface consists of 18 MMRs, which are
Description
Master Transmit FIFO Flush. Set by user to flush the master
Master Busy. Set automatically if the master is busy. Cleared
automatically.
Arbitration Loss. Set in multimaster mode if another master
No ACK. Set automatically if there is no acknowledge of the
address by the slave device. Cleared automatically by
reading the I2C0MSTA register.
Master Receive IRQ. Set after receiving data. Cleared
Master Transmit IRQ. Set at the end of a transmission.
Master Transmit FIFO Underflow. Set automatically if the
master transmit FIFO is underflowing. Cleared
automatically by writing to the I2C0MTX register.
Master TX FIFO Empty. Set automatically if the master
transmit FIFO is empty. Cleared automatically by writing to
Tx FIFO. Cleared automatically once the master Tx FIFO is
flushed. This bit also flushes the slave receive FIFO.
has the bus. Cleared when the bus becomes available.
automatically by reading the I2C0MRX register.
Cleared automatically by writing to the I2C0MTX register.
the I2C0MTX register.
Address
0xFFFF0800
0xFFFF0900
Address
0xFFFF0804
0xFFFF0904
Default Value
0x00
0x00
Default Value
0x01
0x01
Access
R
R
Access
R
R
Rev. A | Page 68 of 92
Table 61. I2C0SSTA MMR Bit Descriptions
Bit
31:15
14
13
12:11
10
9:8
7
6
5
4
3
2
1
0
Value
00
01
10
11
00
01
10
11
Description
Reserved. These bits should be written as 0.
START Decode Bit. Set by hardware if the
device receives a valid START + matching
address. Cleared by an I
or an I
Repeated START Decode Bit. Set by hardware
if the device receives a valid repeated START +
matching address. Cleared by an I
condition, a read of the I2CSSTA register,
or an I
ID Decode Bits.
Received Address Natched ID Register 0.
Received Address Matched ID Register 1.
Received Address Matched ID Register 2.
Received Address Matched ID Register 3.
Stop After Start and Matching Address
Interrupt. Set by hardware if the slave device
receives an I
I
Cleared by a read of the I2C0SSTA register.
General Call ID.
No General Call.
General Call Reset and Program Address.
General Call Program Address.
General Call Matching Alternative ID.
General Call Interrupt. Set if the slave device
receives a general call of any type. Cleared by
setting Bit 8 of the I2CxCFG register. If it is a
general call reset, then all registers are at their
default values. If it is a hardware general call,
then the Rx FIFO holds the second byte of the
general call. This is similar to the I2C0ALT
register (unless it is a general call to reprogram
the device address). For more details, see I
bus specification, version 2.1, Jan. 2000.
Slave Busy. Set automatically if the slave is
busy. Cleared automatically.
No ACK. Set if master asking for data and no
data is available. Cleared automatically by
reading the I2C0SSTA register.
Slave Receive FIFO Overflow. Set automatically
if the slave receive FIFO is overflowing. Cleared
automatically by reading the I2C0SSTA register.
Slave Receive IRQ. Set after receiving data.
Cleared automatically by reading the I2C0SRX
register or flushing the FIFO.
Slave Transmit IRQ. Set at the end of a trans-
mission. Cleared automatically by writing to
the I2C0STX register.
Slave Transmit FIFO Underflow. Set automatically
if the slave transmit FIFO is underflowing.
Cleared automatically by writing to the
I2C0SSTA MMR.
Slave Transmit FIFO Empty. Set automatically if
the slave transmit FIFO is empty. Cleared
automatically by writing to the I2C0STX register.
2
C START condition and matching address.
2
2
C general call reset.
C general call reset.
2
C STOP condition after a previous
2
C STOP condition
2
C STOP
2
C