ADT7320UCPZ AD [Analog Devices], ADT7320UCPZ Datasheet - Page 20

• Manufacturer Part Number: ADT7320UCPZ
• Manufacturer: AD [Analog Devices]

ADT7320
READING DATA
A read transaction begins when the master writes the command
byte to the ADT7320 with the read/write bit set to 1. The master
then supplies 8 or 16 clock pulses, depending on the addressed
register, and the ADT7320 clocks out data from the addressed
register on the DOUT line. Data is clocked out on the first
falling edge of SCLK following the command byte.
The read transaction finishes when the master takes CS high.
The master must begin a new read transaction on the bus for
every register read. Only one register is read per bus transaction.
However, in continuous read mode, Command Byte C2 = 1 and
the temperature value register can be read from continuously.
The master sends 16 clock pulses on SCLK, and the temperature
value is clocked out on DOUT. See Figure 18 and Figure 19.
SCLK
DOUT
DIN
CS
C7
0
DOUT
SCLK
1
DIN
CS
R/W
C6
2
8-BIT COMMAND BYTE
REGISTER ADDR
C5
3
C7
0
C4
1
4
R/W
C6
C3
2
5
8-BIT COMMAND WORD
REGISTER ADDR
CONT
READ
C5
C2
3
6
C4
C1
0
4
7
C3
C0
Figure 18. Read from an 8-Bit Register
0
Figure 19. Read from a 16-Bit Register
5
8
CONT
READ
C2
D15
6
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9
C1
D14
0
7
10
C0
D13
0
8
11
D7
D12
INTERFACING TO DSPs OR MICROCONTROLLERS
The ADT7320 can be operated with CS used as a frame syn-
chronization signal. This scheme is useful for DSP interfaces.
In this case, the first bit (MSB) is effectively clocked out by CS
because CS normally occurs after the falling edge of SCLK in
DSPs. SCLK can continue to run between data transfers,
provided that the timing numbers are obeyed.
CS can be tied to ground and the serial interface can operate in
a 3-wire mode. DIN, DOUT, and SCLK are used to communicate
with the ADT7320 in this mode.
For microcontroller interfaces, it is recommended that SCLK
idle high between data transfers.
SERIAL INTERFACE RESET
The serial interface can be reset by writing a series of 1s on the DIN
input. If a Logic 1 is written to the ADT7320 line for at least 32 serial
clock cycles, the serial interface is reset. This ensures that the interface
can be reset to a known state if the interface gets lost due to a software
error or some glitch in the system. Reset returns the interface to
the state in which it is expecting a write to the communications
register. This operation resets the contents of all registers to their
power-on values. Following a reset, the user should allow a period
of 500 μs before addressing the serial interface.
9
12
D6
D11
10
13
D10
D5
11
14
8-BIT DATA
16-BIT DATA
D4
D9
12
15
D3
Preliminary Technical Data
D8
13
16
D2
D7
14
17
D1
15
D0
16
D2
22
D1
23
D0
24